VLSI Architectures for WIMAX Channel Decoders

This chapter describes the main architectures proposed in the literature to implement the channel decoders required by the WiMax standard, namely convolutional codes, turbo codes (both block and convolutional) and LDPC. Then it shows a complete design of a convolutional turbo code encoder/decoder system for WiMax.Comment: To appear in the book "WIMAX, New Developments", M. Upena, D. Dalal, Y. Kosta (Ed.), ISBN978-953-7619-53-

An Approach for Effective Design Space Exploration of Hard-Decision Viterbi Decoder: Algorithm and VLSI Implementation

Viterbi algorithmic rule is usually used as a cryptography technique for convolutional codes, bit detection technique, Trellis in storage devices. The design space for VLSI implementation of Viterbi decoders is massive, involving selections of turnout, latency, area and power. Even for a set of parameters like constraint length, encoder polynomials and trace-back depth, the task of de-signing a Viterbi decoder is kind of troublesome and needs important effort. Sometimes, as a result of incomplete style area exploration or incorrect analysis, a suboptimal style is chosen. This work analyzes the planning complexness by applying most of the identified VLSI implementation techniques for hard-decision Viterbi cryptography to a distinct set of code parameters. The conclusions square measure supported real styles that actual synthesis and layouts were obtained. In authors’ read, as a result of the depth lined, it is the foremost comprehensive analysis of the subject revealed to this point