A Real time ZigBee Based Locating System

Embedded Systems based on ARM processors are used extensively in mobile devices like PDA’s and MP3 players.ARM is 32bit Reduced Instruction Set Computer(RISC).Windows CE is real time, multi-task operating system that works on a 32-bit processor. This paper suggests Windows CE embedded operating system, and how to build a platform for Windows CE operating system embedded in a LS5310 ARM11 microprocessor S3C6410 and also the design of Windows CE embedded applications based on Embedded VC++ 4.0. Here we are employing RS232 serial port of ARM 11 processor and ZigBee wireless data communications module to design an application for a ZigBee location system with an easy-to-use interface. It performs multiple functions like information and data receiving, saving, processing and display. It has advantages of high performance, low cost, and low power consumption and is an important component of the network locating system

Reliable state retention-based embedded processors through monitoring and recovery

State retention power gating and voltage-scaled state retention are two effective design techniques, commonly employed in embedded processors, for reducing idle circuit leakage power. This paper presents a methodology for improving the reliability of embedded processors in the presence of power supply noise and soft errors. A key feature of the method is low cost, which is achieved through reuse of the scan chain for state monitoring, and it is effective because it can correct single and multiple bit errors through hardware and software respectively. To validate the methodology, ARM Cortex-M0 embedded microprocessor (provided by our industrial project partner) is implemented in FPGA and further synthesized using 65-nm technology to quantify the cost in terms of area, latency and energy. It is shown that the proposed methodology has a small area overhead (8.6%) with less than 4% worst-case increase in critical path and is capable of detecting and correcting both single bit and multi bit errors for a wide range of fault rates

Count three for wear able computers

This paper is a postprint of a paper submitted to and accepted for publication in the Proceedings of the IEE Eurowearable 2003 Conference, and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at the IET Digital Library. A revised version of this paper was also published in Electronics Systems and Software, also subject to Institution of Engineering and Technology Copyright. The copy of record is also available at the IET Digital Library.A description of 'ubiquitous computer' is presented. Ubiquitous computers imply portable computers embedded into everyday objects, which would replace personal computers. Ubiquitous computers can be mapped into a three-tier scheme, differentiated by processor performance and flexibility of function. The power consumption of mobile devices is one of the most important design considerations. The size of a wearable system is often a design limitation

Hardware support for real-time reconfigurable system-on-chip

This paper introduces a computer architecture suitable for embedded real-time applications where low power consumption is a requirement. This is achieved through the use of a hybrid hardware-software system. A system architecture is proposed which allows for modules of a system to be implemented at run-time in either hardware or software. Implementation choices may be made dynamically based on the loading of the host microprocessor, in a multi-tasking environment. An approach to inter-module communication is described, along with how this is affected by dynamic configuration. Some research goals are identified, including investigating the effects on real-time performance, power consumption and the design process involved in reconfigurable systems

Doctor of Philosophy

dissertationAdvancements in process technology and circuit techniques have enabled the creation of small chemical microsystems for use in a wide variety of biomedical and sensing applications. For applications requiring a small microsystem, many components can be integrated onto a single chip. This dissertation presents many low-power circuits, digital and analog, integrated onto a single chip called the Utah Microcontroller. To guide the design decisions for each of these components, two specific microsystems have been selected as target applications: a Smart Intravaginal Ring (S-IVR) and an NO releasing catheter. Both of these applications share the challenging requirements of integrating a large variety of low-power mixed-signal circuitry onto a single chip. These applications represent the requirements of a broad variety of small low-power sensing systems. In the course of the development of the Utah Microcontroller, several unique and significant contributions were made. A central component of the Utah Microcontroller is the WIMS Microprocessor, which incorporates a low-power feature called a scratchpad memory. For the first time, an analysis of scaling trends projected that scratchpad memories will continue to save power for the foreseeable future. This conclusion was bolstered by measured data from a fabricated microcontroller. In a 32 nm version of the WIMS Microprocessor, the scratchpad memory is projected to save ~10-30% of memory access energy depending upon the characteristics of the embedded program. Close examination of application requirements informed the design of an analog-to-digital converter, and a unique single-opamp buffered charge scaling DAC was developed to minimize power consumption. The opamp was designed to simultaneously meet the varied demands of many chip components to maximize circuit reuse. Each of these components are functional, have been integrated, fabricated, and tested. This dissertation successfully demonstrates that the needs of emerging small low-power microsystems can be met in advanced process nodes with the incorporation of low-power circuit techniques and design choices driven by application requirements