Low-pass filtering SC-DAC for reduced jitter and slewing requirements on CTSDMs

In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively combines an infinite impulse response filter with a switched capacitor resistor DAC (SCR-DAC). The resulting DAC is inherently immune toward inter-symbol interference. Moreover, by filtering the feedback signal in the discrete-time domain, the jitter robustness of the modulator is greatly improved and most importantly the slowing requirements on the OpAmps in the modulator's loop filter are greatly relaxed up to a level that the OpAmps can be scaled down toward their ultimate noise limited power level. Furthermore, this LPSC-DAC does not suffer from the SCR-DAC's disadvantageous trade-off between the modulator's jitter, stewing, and anti-aliasing performance. We also show how to compensate for the extra pole of the LPSC-DAC, such that the CTSDM's loop filter, noise- and signal-transfer function remains unchanged. As a result, this technique is completely transparent to the system level designer and established system-level design techniques for sigma delta modulators remain applicable