384 research outputs found
FEEDFORWARD ARTIFICIAL NEURAL NETWORK DESIGN UTILISING SUBTHRESHOLD MODE CMOS DEVICES
This thesis reviews various previously reported techniques for simulating artificial
neural networks and investigates the design of fully-connected feedforward networks
based on MOS transistors operating in the subthreshold mode of conduction as they are
suitable for performing compact, low power, implantable pattern recognition systems.
The principal objective is to demonstrate that the transfer characteristic of the devices
can be fully exploited to design basic processing modules which overcome the linearity
range, weight resolution, processing speed, noise and mismatch of components
problems associated with weak inversion conduction, and so be used to implement
networks which can be trained to perform practical tasks.
A new four-quadrant analogue multiplier, one of the most important cells in the
design of artificial neural networks, is developed. Analytical as well as simulation
results suggest that the new scheme can efficiently be used to emulate both the synaptic
and thresholding functions. To complement this thresholding-synapse, a novel
current-to-voltage converter is also introduced. The characteristics of the well known
sample-and-hold circuit as a weight memory scheme are analytically derived and
simulation results suggest that a dummy compensated technique is required to obtain the
required minimum of 8 bits weight resolution. Performance of the combined load and
thresholding-synapse arrangement as well as an on-chip update/refresh mechanism are
analytically evaluated and simulation studies on the Exclusive OR network as a
benchmark problem are provided and indicate a useful level of functionality.
Experimental results on the Exclusive OR network and a 'QRS' complex detector
based on a 10:6:3 multilayer perceptron are also presented and demonstrate the potential
of the proposed design techniques in emulating feedforward neural networks
A micropower centroiding vision processor
Published versio
Dynamic Power Management for Neuromorphic Many-Core Systems
This work presents a dynamic power management architecture for neuromorphic
many core systems such as SpiNNaker. A fast dynamic voltage and frequency
scaling (DVFS) technique is presented which allows the processing elements (PE)
to change their supply voltage and clock frequency individually and
autonomously within less than 100 ns. This is employed by the neuromorphic
simulation software flow, which defines the performance level (PL) of the PE
based on the actual workload within each simulation cycle. A test chip in 28 nm
SLP CMOS technology has been implemented. It includes 4 PEs which can be scaled
from 0.7 V to 1.0 V with frequencies from 125 MHz to 500 MHz at three distinct
PLs. By measurement of three neuromorphic benchmarks it is shown that the total
PE power consumption can be reduced by 75%, with 80% baseline power reduction
and a 50% reduction of energy per neuron and synapse computation, all while
maintaining temporary peak system performance to achieve biological real-time
operation of the system. A numerical model of this power management model is
derived which allows DVFS architecture exploration for neuromorphics. The
proposed technique is to be used for the second generation SpiNNaker
neuromorphic many core system
A spatial contrast retina with on-chip calibration for neuromorphic spike-based AER vision systems
We present a 32 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels obtained with a diffuser network. This current-based computation produces an important amount of mismatch between neighboring pixels, because the currents can be as low as a few pico-amperes. Consequently, a compact calibration circuitry has been included to trimm each pixel. Measurements show a reduction in mismatch standard deviation from 57% to 6.6% (indoor light). The paper describes the design of the pixel with its spatial contrast computation and calibration sections. About one third of pixel area is used for a 5-bit calibration circuit. Area of pixel is 58 m 56 m, while its current consumption is about 20 nA at 1-kHz event rate. Extensive experimental results are provided for a prototype fabricated in a standard 0.35- m CMOS process.Gobierno de España TIC2003-08164-C03-01, TEC2006-11730-C03-01European Union IST-2001-3412
- …