On the possibility of obtaining MOSFET-like performance and sub-60 mV/decade swing in 1D broken-gap tunnel transistors

Tunneling field-effect transistors (TFETs) have gained a great deal of recent interest due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been achieving high drive currents, which is a prerequisite for high-performance operation. In this paper we explore the performance potential of a 1D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, and the carbon nanotube bandstructure as the model 1D material system. We provide detailed insights into broken-gap TFET (BG-TFET) operation, and show that it can indeed produce less than 60mV/decade subthreshold swing at room temperature even in the presence of electron-phonon scattering. The 1D geometry is recognized to be uniquely favorable due to its superior electrostatic control, reduced carrier thermalization rate, and beneficial quantum confinement effects that reduce the off-state leakage below the thermionic limit. Because of higher source injection compared to staggered-gap and homojunction geometries, BG-TFET delivers superior performance that is comparable to MOSFET's. BG-TFET even exceeds the MOSFET performance at lower supply voltages (VDD), showing promise for low-power/high-performance applications.Comment: 34 pages, 11 figure

Design and Analysis of Robust Low Voltage Static Random Access Memories.

Static Random Access Memory (SRAM) is an indispensable part of most modern VLSI designs and dominates silicon area in many applications. In scaled technologies, maintaining high SRAM yield becomes more challenging since they are particularly vulnerable to process variations due to 1) the minimum sized devices used in SRAM bitcells and 2) the large array sizes. At the same time, low power design is a key focus throughout the semiconductor industry. Since low voltage operation is one of the most effective ways to reduce power consumption due to its quadratic relationship to energy savings, lowering the minimum operating voltage (Vmin) of SRAM has gained significant interest. This thesis presents four different approaches to design and analyze robust low voltage SRAM: SRAM analysis method improvement, SRAM bitcell development, SRAM peripheral optimization, and advance device selection. We first describe a novel yield estimation method for bit-interleaved voltage-scaled 8-T SRAMs. Instead of the traditional trade-off between write and read, the trade-off between write and half select disturb is analyzed. In addition, this analysis proposes a method to find an appropriate Write Word-Line (WWL) pulse width to maximize yield. Second, low leakage 10-T SRAM with speed compensation scheme is proposed. During sleep mode of a sensor application, SRAM retaining data cannot be shut down so it is important to minimize leakage in SRAM. This work adopts several leakage reduction techniques while compensating performance. Third, adaptive write architecture for low voltage 8-T SRAMs is proposed. By adaptively modulating WWL width and voltage level, it is possible to achieve low power consumption while maintaining high yield without excessive performance degradation. Finally, low power circuit design based on heterojunction tunneling transistors (HETTs) is discussed. HETTs have a steep subthreshold swing beneficial for low voltage operation. Device modeling and design of logic and SRAM are proposed.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91569/1/daeyeonk_1.pd

Power Modeling and Optimization for GPGPUs

Modern graphics processing units (GPUs) supports tens of thousands of parallel threads and delivers remarkably high computing throughput. General-Purpose computing on GPUs (GPGPUs) is becoming the attractive platform for general-purpose applications that request high computational performance such as scientific computing, financial applications, medical data processing, and so on. However, GPGPUs is facing severe power challenge due to the increasing number of cores placed on a single chip with decreasing feature size. In order to explore the power optimization techniques in GPGPUs, I first build a power model for GPGPUs, which is able to estimate both dynamic and leakage power of major microarchitecture structures in GPGPUs. I then target on the power-hungry structures (e.g. register file) to explore the energy-efficient GPGPUs. In order to hide the long latency operations, GPGPUs employs the fine-grained multi-threading among numerous active threads, leading to the sizeable register files with massive power consumption. The conventional method to reduce dynamic power consumption is the supply voltage scaling. And the inter-bank tunneling FETs (TFETs) is the promising candidate compared to CMOS for low voltage operations regarding to both leakage and performance. However, always executing at the low voltage will result in significant performance degradation. In this study, I propose the hybrid CMOS-TFET based register file and allocate TFET-based registers to threads whose execution progress can be delayed to some degree to avoid the memory contentions with other threads to reduce both dynamic and leakage power, and the CMOS-based registers are still used for threads requiring normal execution speed. My experimental results show that the proposed technique achieves 30% energy (including both dynamic and leakage) reduction in register files with negligible performance degradation compared to the baseline case equipped with naive power optimization technique

CMOS 소자와 함께 쓸 수 있는 실리콘 나노선 터널링 전계효과 트랜지스터

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 박병국.향후 CMOS 기술의 축소화에 따른 소자의 소비전력증가 문제를 해결하고 0.5 V 이하의 동작전압으로도 저전력 동작하는 스위칭 소자를 개발하기 위해, 기존 CMOS 기술을 변형한 집적방법으로 실리콘 나노와이어 밴드간-터널링 전계효과 트랜지스터(band-to-band tunneling field-effect transistorTFET)와 금속-산화막-반도체 전계효과 트랜지스터(metal-oxide-semiconductor field-effect transistorMOSFET)를 동시집적하고 소자로써 동작을 확인하였다. TFET은 동작원리상 소스 영역의 에너지의 상한 값이 제한되어 있는 가전자대의 전자가 터널링에 의해 캐리어가 채널로 주입되므로 상온에서 MOSFET 보다 훨씬 작은 게이트 전압변화로 소자를 켤 수 있는 특징이 있다. 이 소자에서 터널링을 촉진하려면 소스/채널간 접합을 적은 공핍에도 쉽게 켤 수 있어야 하므로 게이트 산화막의 두께, 나노와이어의 선폭, 측벽 스페이서의 폭이 작아야 하고 접합주변에서 불순물 농도가 급격히 변해야 함을 이론적인 TCAD 시뮬레이션 연구를 통해 알 수 있었다. 이론적 연구를 바탕으로, 소스와 드레인의 극성이 서로 다른 TFET을 집적하기 위해 기존의 CMOS 집적방법에 자가정렬 비대칭 소스/드레인을 형성하는 집적방법 (integration scheme for self-aligned asymmetric source/drain)을 추가하여 MOSFET과 TFET을 SOI 기판 위에 동시집적 하였다. 최적화된 전자선 리소그래피공정 (electron-beam lithography)과 새로 개발한 화학적 코너 라운딩 (chemical corner-rounding) 방법을 적용하여 최소 선폭 14.5 nm의 반실린더형 나노와이어를 성공적으로 형성하였다. 측벽 스페이서는 질화막과 산화막으로 폭 20 nm로 형성하여, 액티브 영역의 손상을 최소화하여 자가정렬된 니켈 실리사이드 (self-aligned nickel silicide)를 형성하는데 문제가 없도록 하면서도 측벽 스페이서의 선폭을 최소화할 수 있도록 하였다. 접합의 농도가 급변하게 하기 위해서 니켈 실리사이드에 의한 스노플라우 효과 (snowploughing effect)를 이용하였다. 이를 통해 게이트 길이 1 μm인 장채널 TFET과 150 ~ 28 nm의 단채널 TFET들이 자기정렬 방식으로 성공적으로 제작되었다. 제작된 소자의 측정결과 n+/진성 경계가 p+/진성 경계에서보다 불순물 농도가 더 급격하도록 만들어진 것을 확인하였고, 따라서 TFET은 p-채널 모드로 더 잘 동작하였다. 장채널소자에서는 순간기울기 기준 47 mV/decade 로 동작하는 소자가 만들어진 것을 확인하였으며, 단채널 TFET으로는 MOSFET의 경우처럼 채널길이가 짧아질 수록 게이트의 채널제어능력이 나빠지는 단채널효과가 TFET에도 존재함을 확인하였다. 단채널효과는 나노와이어의 선폭이 작아진 경우 감소하였는데 나노와이어 선폭 19.5 nm이고 게이트 선폭이 109 nm인 소자에서 62 mV/decade의 양호한 TFET 동작특성을 보였다. 이와 더불어 채널방향에 따른 소자 특성개선 가능성과 반실린더형 채널구조를 이용한 기판전압에 의한 소자특성 조절에 대한 가능성을 제작된 소자로부터 검토하였다. 이상의 결과에서 기존 CMOS 기술을 변형하는 방식으로 MOSFET과 TFET을 동시집적함으로써 좀 더 양산가능성 높은 TFET 제작 방법을 제시 하였으며 향후 MOSFET-TFET 혼성회로를 이용한 미래 CMOS 회로의 저전력화 가능성을 제시하였다.In order to develop practical low-power switching devices operating at a voltage below 0.5 V and solve the power density problem of highly-scaled CMOS technology, the silicon nanowire band-to-band tunneling field-effect transistors (TFETs) and conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) are co-integrated with a modified CMOS flow and their electrical functionalities are confirmed. Since the carrier injection in a TFET system occurs by tunneling of valence-band electrons, it can operate without leakage issue and the gate bias swing to switch the device can be very small. In spite of the fancy operating principles, however, the replacement of MOSFETs with TFETs is not likely to happen in near future. This is because the difference of source/drain (S/D) polarities and current-flow directionality issues make TFETs not suitable for the existing MOSFET-based CMOS circuits but demanding new circuit topologies. Therefore the TFETs that can be co-integrated with MOSFETs are selected as the topic of this work. From the theoretical study with a TCAD device simulator, the gate insulator thickness, nanowire width, abruptness of doping profile near the source/channel boundary and the design of sidewall spacer width are found to be critical to reducing the tunneling barrier width to increase the current. Design concepts learned from TCAD simulation studies are implemented to fabrication with a novel integration scheme for self-aligned asymmetric S/D. By inserting the process steps to form the asymmetric S/D to the conventional CMOS process flow, MOSFETs and TFETs are successfully co-integrated on the same silicon-on-insulator substrate. Through newly developed and optimized processes such as reduced-repulsion electron-beam lithography, chemical corner-rounding, tight sidewall spacer etch, and two-step self-aligned nickel silicide process, the TFETs with L = 1 μm ~ 28 nm, minimum W = 14.5 nm, 20 nm dual sidewall spacer, and dopant-segregated steep doping profile are successfully fabricated. From the electrical measurement of gate-induced drain leakage (GIDL) of the co-integrated MOSFETs, the impurity profile near the n+/intrinsic boundary is found to be much more abrupt than near p+/intrinsic boundary. Therefore, the fabricated TFETs operate better as a p-channel device rather than n-channel device. The long-channel device shows good switching characteristics of 47 mV/decade. Short-channel effect similar to that of MOSFETs is experimentally observed for TFETs. It is also demonstrated that the short-channel effect can be reduced by improving electrostatics, with a thinner-nanowire device with L = 109 nm. Substrate-bias controllability of TFETs and its extension to nanowire TFETs are examined in the comparison with MOSFETs. Possibilities to improve current drivability by controlling tunneling process with the channel direction are explored with both planar and nanowire TFETs. From this study, it is demonstrated that TFETs can be co-integrated with CMOS devices in a more manufacturable way by introducing a self-aligned integration scheme to conventional process flow. This work also opens a possibility of a new low-power design technology using MOSFET/TFET hybrid circuits.Chapter 1 Introduction 1 1.1 Origin of Power Crisis in CMOS Technologies .......................... 1 1.2 Tunneling Field-Effect Transistors (TFETs) ............................... 3 1.3 Replacer or Complementor? ....................................................... 5 1.4 Previous Studies .......................................................................... 7 1.5 Thesis Outline ............................................................................. 9 Chapter 2 Theoretical Studies 11 2.1 Basic Operations of TFETs ....................................................... 11 2.2 Nanowire TFETs ...................................................................... 15 2.3 Device Design Factors and Variability ..................................... 17 2.4 Operation Range Where TFETs Beat MOSFETs ..................... 25 2.5 Summary of the Target Device ................................................. 27 Chapter 3 Device Fabrication 29 3.1 Key Process Designs and Fabrication Flow ............................. 29 3.2 Patterning and Rounding of Nanowire Active Regions ........... 31 3.3 Self-aligned Formation of Gate and Asymmetric S/D Regions 35 3.4 Sidewall Spacer and Self-aligned Silicide Processes................ 38 Chapter 4 Device Characteristics 42 4.1 Fabricated Metal-Oxide-Semiconductor Capacitor ................. 42 4.2 Junction Properties of Co-Integrated MOSFETs ...................... 44 4.3 Transfer and Output Characteristics of TFETs ......................... 48 4.4 Device Properties with Design Partitionings ........................... 54 4.4.1 Active Width .............................................................. 54 4.4.2 Channel Length .......................................................... 55 4.4.3 Channel Direction ...................................................... 60 4.4.4 Back-Gate Effect ........................................................ 64   Chapter 5 Conclusions 67 5.1 Conclusions .............................................................................. 67 5.2 Suggestions for Future Work .................................................. 69 Bibliography....................................................................... 71 Appendixes ......................................................................... 82 Abstract in Korean ............................................................ 87 Acknowledgements ............................................................ 90Docto

Vertical Silicon Nanowire Gate-All-Around Tunneling Field Effect Tranistors for Future Low Power Nanoelectronics

Master'sMASTER OF ENGINEERIN

Low power circuit design based on heterojunction tunneling transistors (HETTs)

The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low supply voltages. This paper investigates extremely-low power circuits based on new Si/SiGe HEterojunction Tunneling Transistors (HETTs) that have subthreshold swing < 60 mV/decade. Device characteristics as determined through Technology Computer Aided Design (TCAD) tools are used to develop a Verilog-A device model to simulate and evaluate a range of HETT-based circuits. We show that a HETT-based ring oscillator (RO) shows a 9−19X reduction in dynamic power compared to a CMOS RO. We also explore two key differences between HETTs and traditional MOSFETs, namely asymmetric current flow and increased Miller capacitance, analyzing their effect on circuit behavior and proposing methods to address them. Finally, HETT characteristics have the most dramatic impact on SRAM operation and hence we propose a novel 7-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow. This new HETT SRAM design achieves 7−37X reduction in leakage power compared to CMOS

Simulation of Double-Gate Silicon Tunnel FETs with a High-k Gate Dielectric

The down-scaling of conventional MOSFETs has led to an impending power crisis, in which static power consumption is becoming too high. In order to improve the energy-efficiency of electronic circuits, small swing switches are interesting candidates to replace or complement the MOSFETs used today. Tunnel FETs, which are gated p-i-n diodes whose on-current arises from band-to-band tunneling, are attractive new devices for low-power applications due to their low off-current and their potential for a small subthreshold swing. The numerical simulations presented in this thesis have been carried out using a non-local band-to-band tunneling model in Silvaco Atlas. Numerical simulations based on correct underlying models are important for emerging devices, since they can provide insights about optimization before fabrication is carried out, can aid the understanding of device physics through 1D and 2D cross sections, and can be the basis for the formation of an accurate compact model. In general, only CMOS-compatible materials and structures have been used in the Tunnel FET designs presented here. One goal of this thesis was to stay within the framework of what is possible in standard industrial nanoelectronics cleanrooms today, without requiring processes whose mastery lies many years in the future. For this reason, the focus of this thesis is on all-silicon devices, and heterostructures that incorporate other materials are only mentioned. In chapter three, the optimization of the static characteristics of a Tunnel FET is carried out, looking at gate structure (single or double), doping levels of each device region, gate dielectric permittivity, and silicon body thickness. A study of the reduction of the band gap at the tunnel junction is also presented, showing the resulting improvement in on-current and subthreshold swing. Chapter four introduces a new method for threshold voltage extraction in Tunnel FETs. This method has one key advantage over the commonly-used constant current threshold voltage extraction technique: it has a physical meaning. The transconductance method, which has already been used for conventional MOSFETs, pinpoints the Tunnel FET voltage at which the transition from strong control to weak control of the tunneling energy barrier width, and therefore the on-current, takes place. This is analogous to the threshold voltage in a conventional MOSFET which marks the transition from weak inversion to strong inversion at φs=2φF. It is found that Tunnel FETs have two threshold voltages, one in relation to the gate voltage, and the second in relation to the drain voltage, and each depends on the voltage applied at the opposite terminal. A length scaling study is carried out in chapter five, demonstrating the scaling limits of Tunnel FETs at gate lengths on the order of 10-20 nm, due to p-i-n diode leakage current that degrades the off-current. Tunnel FETs designed to have better electrostatic control of the tunnel junction by the gate can scale further before they hit this diode leakage limit at some small gate length. Chapter six presents an additive booster strategy for Tunnel FET optimization, and then uses the resulting optimized device as the basis of a parameter variation study. Here, one parameter is varied at a time, and the effects on the important characteristics (subthreshold swing, threshold voltage, and on-current) are evaluated. The parameters requiring the most control during fabrication are identified. Since Tunnel FETs are emerging devices, the most important future work will be to fabricate fully-optimized n- and p-type devices, and to develop accurate compact models for their incorporation into circuits

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts