2 research outputs found
QoS support in embedded networks and NoC
Quality of service (QoS) requirements such as priorities, packet delivery and packet delivery time are important and critical for embedded networks and networkson-chip (NoC) [1]. We consider mechanisms for QoS support in the SpaceFibre, SpaceWire and GigaSpaceWire protocols, possibility of using them in embedded networks and NoC. In the article we analyze approaches for QoS provision, their feasibility and value of QoS in SpaceWire/GigaSpaceWire and in SpaceFibre networks. Networks with different topologies and traffic pattern are used to study and to evaluate the performance. Various traffic types such as the data packets, streaming data, commands will be transmitted in networks. Data delivery characteristics for SpaceFibre and SpaceWire/GigaSpaceWire networks are analyzed and compared. Also we compare characteristics that are achievable in NoC, which are based on QoS mechanisms of SpaceFibre, SpaceWire and GigaSpaceWire. Hardware costs are one of the main constraints for embedded networks and NoC. Therefore we compare hardware costs of basic SpaceFibre, SpaceWire and GigaSpaceWire routers
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Network-on-Chip Synchronization
Technology scaling has enabled the number of cores within a System on Chip (SoC) to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using Dynamic Voltage and Frequency Scaling (DVFS) operate each of these cores on distinct and dynamic clock domains. The main communication method between these cores is increasingly more likely to be a Network-on-Chip (NoC). Typically, the interfaces between these clock domains experience multi-cycle synchronization latencies due to their use of “brute-force” synchronizers. This dissertation aims to improve the performance of NoCs and thereby SoCs as a whole by reducing this synchronization latency.
First, a survey of NoC improvement techniques is presented. One such improvement technique: a multi-layer NoC, has been successfully simulated. Given how one of the most commonly used techniques is DVFS, a thorough analysis and simulation of brute-force synchronizer circuits in both current and future process technologies is presented. Unfortunately, a multi-cycle latency is unavoidable when using brute-force synchronizers, so predictive synchronizers which require only a single cycle of latency have been proposed.
To demonstrate the impact of these predictive synchronizer circuits at a high level, multi-core system simulations incorporating these circuits have been completed. Multiple forms of GALS NoC configurations have been simulated, including multi-synchronous, NoC-synchronous, and single-synchronizer. Speedup on the SPLASH benchmark suite was measured to directly quantify the performance benefit of predictive synchronizers in a full system. Additionally, Mean Time Between Failures (MTBF) has been calculated for each NoC synchronizer configuration to determine the reliability benefit possible when using predictive synchronizers