2 research outputs found
Design of Frequency Divider (FD/2 and FD 2/3) Circuits for a Phase Locked Loop
This paper reports on three design of Frequency Divider (FD/2) and Frequency Divider (FD 2/3) circuits. Tanner EDA tool developed on 130nm CMOS technology with a voltage supply of 1.3 V is used to build, model, and compare all circuits. For the FD/2 circuit, E-TSPC Pass Transistor logic uses 1.77 µW, whereas TSPC logic consumes 5.57 µW for the FD 2/3 circuit. It implies that the TSPC logic is the best solution since it meets the speed and power consumption requirements
Low power design of 16-bit synchronous counter by introducing effective clock monitoring circuits
Most of the system-level designs contain sequential circuits. Power optimization of these circuits at many levels is
required to build a portable device with a long battery life. A dynamic clock gating technique was used in this work to reduce the
power and temperature of a 16-bit counter. The simulation was performed on cadence SCL 180 nm technology, for a supply
voltage of 1.8 V at a frequency of 500 MHz. With the proposed approach, a 77.16% power reduction was achieved at the cost of
14.83% in area overhead. Moreover, the layout of the circuits was also designed in the Innovus tool to obtain a more accurate
silicon area and gate count. The Innovus output files ".flp file" and ".pptrace file" were used as inputs to the HotSpot tool for
determining the absolute temperature of the integrated circuits (ICs). The obtained temperature results were compared with the
ordinary 16-bit counter, and it was found that the proposed approach was able to reduce temperature by 14.34%