Asynchronous techniques for system-on-chip design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed

Asynchronous Nano-Electronics: Preliminary Investigation

This paper is a preliminary investigation in implementing asynchronous QDI logic in molecular nano-electronics, taking into account the restricted geometry, the lack of control on transistor strengths, the high timing variations. We show that the main building blocks of QDI logic can be successfully implemented; we illustrate the approach with the layout of an adder stage. The proposed techniques to improve the reliability of QDI apply to nano-CMOS as well

Serialized Asynchronous Links for NoC

This paper proposes an asynchronous serialized link for NoC that can achieve the same levels of performance in terms of flits per second as a synchronous link but with a reduced number of wires in the point to point switch links and reduced power consumption. This is achieved by employing serialization in the asynchronous domain as opposed to synchronous to facilitate the removal of global clocking on the serial links. Based on transistor level simulations using 0.12 ?m foundry models it has been shown that it is possible to achieve the same level of performance as synchronous but with 75% reduction in wires and 65% reduction in power for a 300 MFlit/s link with 8 buffers with a switch clock speed of 300 MHz. Furthermore the paper presents the design requirements arising from interfacing switches of synchronous NoC and asynchronous serial links

Magnetic wire as stress controlled micro-rheometer for cytoplasm viscosity measurements

We review here different methods to measure the bulk viscosity of complex fluids using micron-sized magnetic wires. The wires are characterized by length of a few microns and diameter of a few hundreds of nanometers. We first draw analogies between cone-and-plate rheometry and wire-based microrheology. In particular we highlight that magnetic wires can be operated as stress-controlled rheometers for two types of testing, the creep-recovery and steady shear experiments. In the context of biophysical applications, the cytoplasm of different cell lines including fibroblasts, epithelial and tumor cells is studied. It reveals that the interior of living cells can be described as a viscoelastic liquid with a static viscosity comprised between 10 and 100 Pas. We extend the previous approaches and show that the proposed technique can also provide time resolved viscosity data, which for cells display strong temporal fluctuations. The present work demonstrates the high potential of the magnetic wires for quantitative rheometry in confined espaces.Comment: 11 pages, 6 figures, 40 reference

Adaptive Latency Insensitive Protocols

Latency-insensitive design copes with excessive delays typical of global wires in current and future IC technologies. It achieves its goal via encapsulation of synchronous logic blocks in wrappers that communicate through a latency-insensitive protocol (LIP) and pipelined interconnects. Previously proposed solutions suffer from an excessive performance penalty in terms of throughput or from a lack of generality. This article presents an adaptive LIP that outperforms previous static implementations, as demonstrated by two relevant cases — a microprocessor and an MPEG encoder — whose components we made insensitive to the latencies of their interconnections through a newly developed wrapper. We also present an informal exposition of the theoretical basis of adaptive LIPs, as well as implementation detail

Unordered Error-Correcting Codes and their Applications

We give efficient constructions for error correcting unordered {ECU) codes, i.e., codes such that any pair of codewords are at a certain minimal distance apart and at the same time they are unordered. These codes are used for detecting a predetermined number of (symmetric) errors and for detecting all unidirectional errors. We also give an application in parallel asynchronous communications

Coding for skew-tolerant parallel asynchronous communications

A communication channel consisting of several subchannels transmitting simultaneously and asynchronously is considered, an example being a board with several chips, where the subchannels are wires connecting the chips and differences in the lengths of the wires can result in asynchronous reception. A scheme that allows transmission without an acknowledgment of the message, therefore permitting pipelined communication and providing a higher bandwidth, is described. The scheme allows a certain number of transitions from a second message to arrive before reception of the current message has been completed, a condition called skew. Necessary and sufficient conditions for codes that can detect skew as well as for codes that are skew-tolerant, i.e. can correct the skew and allow continuous operation, are derived. Codes that satisfy the necessary and sufficient conditions are constructed, their optimality is studied, and efficient decoding algorithms are devised. Potential applications of the scheme are in on-chip, on-board, and board to board communications, enabling much higher communication bandwidth

A Universal Semi-totalistic Cellular Automaton on Kite and Dart Penrose Tilings

In this paper we investigate certain properties of semi-totalistic cellular automata (CA) on the well known quasi-periodic kite and dart two dimensional tiling of the plane presented by Roger Penrose. We show that, despite the irregularity of the underlying grid, it is possible to devise a semi-totalistic CA capable of simulating any boolean circuit on this aperiodic tiling.Comment: In Proceedings AUTOMATA&JAC 2012, arXiv:1208.249

Delay-insensitive pipelined communication on parallel buses

Consider a communication channel that consists of several subchannels transmitting simultaneously and asynchronously. As an example of this scheme, we can consider a board with several chips. The subchannels represent wires connecting between the chips where differences in the lengths of the wires might result in asynchronous reception. In current technology, the receiver acknowledges reception of the message before the transmitter sends the following message. Namely, pipelined utilization of the channel is not possible. Our main contribution is a scheme that enables transmission without an acknowledgment of the message, therefore enabling pipelined communication and providing a higher bandwidth. However, our scheme allows for a certain number of transitions from a second message to arrive before reception of the current message has been completed, a condition that we call skew. We have derived necessary and sufficient conditions for codes that can tolerate a certain amount of skew among adjacent messages (therefore, allowing for continuous operation) and detect a larger amount of skew when the original skew is exceeded. These results generalize previously known results. We have constructed codes that satisfy the necessary and sufficient conditions, studied their optimality, and devised efficient decoding algorithms. To the best of our knowledge, this is the first known scheme that permits efficient asynchronous communications without acknowledgment. Potential applications are in on-chip, on-board, and board to board communications, enabling much higher communication bandwidth