Sequential circuit design in quantum-dot cellular automata

In this work we present a novel probabilistic modeling scheme for sequential circuit design in quantum-dot cellular automata(QCA) technology. Clocked QCA circuits possess an inherent direction for flow of information which can be effectively modeled using Bayesian networks (BN). In sequential circuit design this presents a problem due to the presence of feedback cycles since BN are direct acyclic graphs (DAG). The model presented in this work can be constructed from a logic design layout in QCA and is shown to be a dynamic Bayesian Network (DBN). DBN are very powerful in modeling higher order spatial and temporal correlations that are present in most of the sequential circuits. The attractive feature of this graphical probabilistic model is that that it not only makes the dependency relationships amongst node explicit, but it also serves as a computational mechanism for probabilistic inference. We analyze our work by modeling clocked QCA circuits for SR F/F, JK F/F and RAM designs

Hierarchical probabilistic macromodeling for QCA circuits

With the goal of building an hierarchical design methodology for quantum-dot cellular automata (QCA) circuits, we put forward a novel, theoretically sound, method for abstracting the behavior of circuit components in QCA circuit, such as majority logic, lines, wire-taps, cross-overs, inverters, and corners, using macromodels. Recognizing that the basic operation of QCA is probabilistic in nature, we propose probabilistic macromodels for standard QCA circuit elements based on conditional probability characterization, defined over the output states given the input states. Any circuit model is constructed by chaining together the individual logic element macromodels, forming a Bayesian network, defining a joint probability distribution over the whole circuit. We demonstrate three uses for these macromodel-based circuits. First, the probabilistic macromodels allow us to model the logical function of QCA circuits at an abstract level - the "circuit" level - above the current practice of layout level in a time and space efficient manner. We show that the circuit level model is orders of magnitude faster and requires less space than layout level models, making the design and testing of large QCA circuits efficient and relegating the costly full quantum-mechanical simulation of the temporal dynamics to a later stage in the design process. Second, the probabilistic macromodels abstract crucial device level characteristics such as polarization and low-energy error state configurations at the circuit level. We demonstrate how this macromodel-based circuit level representation can be used to infer the ground state probabilities, i.e., cell polarizations, a crucial QCA parameter. This allows us to study the thermal behavior of QCA circuits at a higher level of abstraction. Third, we demonstrate the use of these macromodels for error analysis. We show that low-energy state configurations of the macromodel circuit match those of the layout level, thus allowing us to isolate weak p- oints in circuits design at the circuit level itsel

Bayesian macromodeling for circuit level QCA design

We present a probabilistic methodology to model and abstract the behavior of quantum-dot cellular automata circuit(QCA) at “ circuit level” above the current practice of layout level. These macromodels provide input-output relationship of components (a set of QCA cells emulating a logical function) that are faithful to the underlying quantum effects. We show the macromodeling of a few key circuit components in QCA circuit, such as majority logic, lines, wire-taps, cross-overs, inverters, and corners. In this work, we demostrate how we can make use of these macromodels to abstract the logical function of QCA circuits and to extract crucial device level characteristics such as polarization and low-energy error state configurations by circuit level Bayesian model, accurately accounting for temperature and other device level parameters. We also demonstrate how this macromodel based design can be used effectively in analysing and isolating the weak spots in the design at circuit level itself

Modeling the input history of programs for improved instruction-memory performance

When a program is loaded into memory for execution, the relative position of its basic blocks is crucial, since loading basic blocks that are unlikely to be executed first places them high in the instruction-memory hierarchy only to be dislodged as the execution goes on. In this paper we study the use of Bayesian networks as models of the input history of a program. The main point is the creation of a probabilistic model that persists as the program is run on different inputs and at each new input refines its own parameters in order to reflect the program's input history more accurately. As the model is thus tuned, it causes basic blocks to be reordered so that, upon arrival of the next input for execution, loading the basic blocks into memory automatically takes into account the input history of the program. We report on extensive experiments, whose results demonstrate the efficacy of the overall approach in progressively lowering the execution times of a program on identical inputs placed randomly in a sequence of varied inputs. We provide results on selected SPEC CINT2000 programs and also evaluate our approach as compared to the gcc level-3 optimization and to Pettis-Hansen reordering