A Survey on Flip Flop Replacement to Latch on Various Design

This paper presents survey for the replacement of flip flop to latches and the advantages of the latch based sequential design Flip flop are the major part of the design a sequential elements and this flip flop has more disadvantages as performance decreases and area increases. An alternate method to increase the performance and reduce the area size latches. Latches are used instead of flip flops in certain places to increase the performance and decrease the area

A Survey on Flip Flop Replacement to Latch on Various Design

This paper presents survey for the replacement of flip flop to latches and the advantages of the latch based sequential design Flip flop are the major part of the design a sequential elements and this flip flop has more disadvantages as performance decreases and area increases. An alternate method to increase the performance and reduce the area size latches. Latches are used instead of flip flops in certain places to increase the performance and decrease the area

Latch-based Performance Optimization for FPGAs

We explore using pulsed latches for timing optimization -- a first in the academic FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (i.e. not 50%) duty cycle. As latches are already present on commercial FPGAs, their use for timing optimization can avoid the power or area drawbacks associated with other techniques such as clock skew and retiming. We propose algorithms that automatically replace certain flip-flops with latches for performance gains. Under conservative short path or minimum delay assumptions, our latch-based optimization, operating on already routed designs, provides all the benefit of clock skew in most cases and increases performance by 9%, on average, essentially for "free". We show that short paths greatly hinder the ability of using pulsed latches, and further improvements in performance are possible by increasing the delay of certain short paths.MAS