A Novel Real-time Approach to Unified Power Flow Controller Validation

This paper presents the development of a real-time hardware/software laboratory to interface a soft real-time power system simulator with multiple unified power flow controllers (UPFC) via hardware-in-the-loop (HIL) to study their dynamic responses and validate control and placement approaches. This paper describes a unique laboratory facility that enables large-scale, soft real-time power system simulation coupled with the true physical behavior of a UPFC as opposed to the controller response captured by many other real-time simulators. The HIL line includes a synchronous machine, a UPFC, and a programmable load to reproduce the physical dynamics of the UPFC sub-network

Disaster-Resilient Control Plane Design and Mapping in Software-Defined Networks

Communication networks, such as core optical networks, heavily depend on their physical infrastructure, and hence they are vulnerable to man-made disasters, such as Electromagnetic Pulse (EMP) or Weapons of Mass Destruction (WMD) attacks, as well as to natural disasters. Large-scale disasters may cause huge data loss and connectivity disruption in these networks. As our dependence on network services increases, the need for novel survivability methods to mitigate the effects of disasters on communication networks becomes a major concern. Software-Defined Networking (SDN), by centralizing control logic and separating it from physical equipment, facilitates network programmability and opens up new ways to design disaster-resilient networks. On the other hand, to fully exploit the potential of SDN, along with data-plane survivability, we also need to design the control plane to be resilient enough to survive network failures caused by disasters. Several distributed SDN controller architectures have been proposed to mitigate the risks of overload and failure, but they are optimized for limited faults without addressing the extent of large-scale disaster failures. For disaster resiliency of the control plane, we propose to design it as a virtual network, which can be solved using Virtual Network Mapping techniques. We select appropriate mapping of the controllers over the physical network such that the connectivity among the controllers (controller-to-controller) and between the switches to the controllers (switch-to-controllers) is not compromised by physical infrastructure failures caused by disasters. We formally model this disaster-aware control-plane design and mapping problem, and demonstrate a significant reduction in the disruption of controller-to-controller and switch-to-controller communication channels using our approach.Comment: 6 page

Optimization of Battery Energy Storage to Improve Power System Oscillation Damping

A placement problem for multiple Battery Energy Storage System (BESS) units is formulated towards power system transient voltage stability enhancement in this paper. The problem is solved by the Cross-Entropy (CE) optimization method. A simulation-based approach is adopted to incorporate higher-order dynamics and nonlinearities of generators and loads. The objective is to maximize the voltage stability index, which is setup based on certain grid-codes. Formulations of the optimization problem are then discussed. Finally, the proposed approach is implemented in MATLAB/DIgSILENT and tested on the New England 39-Bus system. Results indicate that installing BESS units at the optimized location can alleviate transient voltage instability issue compared with the original system with no BESS. The CE placement algorithm is also compared with the classic PSO (Particle Swarm Optimization) method, and its superiority is demonstrated in terms of a faster convergence rate with matched solution qualities.Comment: This paper has been accepted by IEEE Transactions on Sustainable Energy and now still in online-publication phase, IEEE Transactions on Sustainable Energy. 201

An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

© 2015 IEEE.Leakage power is an important component of the total power consumption in field-programmable gate arrays (FPGAs) built using 90-nm and smaller technology nodes. Power gating was shown to be effective at reducing the leakage power. Previous techniques focus on turning OFF unused FPGA resources at configuration time; the benefit of this approach depends on resource utilization. In this paper, we present an FPGA architecture that enables dynamically controlled power gating, in which FPGA resources can be selectively powered down at run-time. This could lead to significant overall energy savings for applications having modules with long idle times. We also present a CAD flow that can be used to map applications to the proposed architecture. We study the area and power tradeoffs by varying the different FPGA architecture parameters and power gating granularity. The proposed CAD flow is used to map a set of benchmark circuits that have multiple power-gated modules to the proposed architecture. Power savings of up to 83% are achievable for these circuits. Finally, we study a control system of a robot that is used in endoscopy. Using the proposed architecture combined with clock gating results in up to 19% energy savings in this application