New Front-end DSP Algorithms and VLSI Architectures for Cost-efficient Communication Receiver IC Designs

混合訊號的設計 (Mixed-Signal Design) 在通訊基頻電路 (Baseband Circuit)中是不可避免的趨勢，因為它能降低硬體的複雜度與減少晶片間的介面。混合訊號的設計最困難的部分往往是在介面的元件，以及數位─類比間的電路。它必須應用許多數位訊號處理的技巧以控制類比元件。我們歸納這部分的電路為「前端數位訊號處理」(Front-end Digital Signal Processing)。在本論文中，我們將會針對有線與無線通訊系統，宏觀的討論與設計前端數位訊號處理。 首先，我們分析在有線與無線通訊應用中，前端訊號處理器的困難與瓶頸。對於有線通訊系統，我們研究前端訊號處理電路中的自動增益控制器 (Automatic Gain Control) 和等化器 (Equalizer)。傳統的自動增益控控制器，需要額外的時間計算平均能量或者最大峰值(peak-to-average power ratio, PAPR)，這會增加硬體複雜度，浪費很長的時間。另外，傳統的做法也會因為碼間干擾(Intersymbol Interference, ISI)使準確度降低。 在本論文，我們提出了增益等化器的架構，其數位控制單元(Digial Control Unit, DCU) 面積只有約傳統電路的十分之一。而且對於任何的碼間干擾，其輸出的能量都可以達到最佳的峰均功率比。此外，我們也提供了增益等化器收斂行為的分析。結果顯示，其收斂時間僅僅是傳統盲目等化器 (Blind Equalizer) 的一半。這個架構已經在快速乙太網路 (Fast Ethernet) 的實際晶片中得到驗證，使用Faraday/UMC 0.18um library。測試結果顯示，其錯誤位元率 (Bit Error Rate) 優於802.3u的要求。而這個架構也通過University of New Hampshire InterOperability Laboratory的Killer pattern測試。 對於無線通訊系統，我們則是研究多頻道正交頻率多工系統（Multiband orthogonal frequency-division multiplexing, MB-OFDM）之訊號處理前端中的自動增益控制器與封包檢測器 (Packet Detector)。正交頻率多工系統使用跳頻 (Frequency Hopping) 方式達到多工(Multiple Access)與頻率多樣 (Frequency Diversity) 的目的。但因此卻會造成封包檢測器的設計困難與時頻碼 (Time Frequency Code) 同步的問題。這都會造成硬體成本的增加與接收器靈敏度上升。在本文論中，我們首先會有系統的分析多頻道正交頻率多工系統與傳統正交頻率多工系統的不同，接著，提出頻道追蹤封包檢測器（Band Tracking Packet Detector, BT-PD）。它可對抗訊雜比只有-8.4dB的最糟狀況的多路徑通道 (Multipath Channel)，而封包檢測錯誤率 ( Packet Detection Error Rate) 只有10-5。此外，我們也提出了幾種低成本的硬體架構設計，例如分「W-H分解法」（Walsh-Hadamard Decomposition）、「僅用Preamble係數符號法」（Only Sign-bit remain in preamble coefficient）、「廣播式FIR濾波器設計」（Broadcasting FIR filter design）、「假因果紓解法」(Pseudo Non-Causal Relax) 等等架構。最後分析得知，此一系列低複雜度的電路架構，其電路面積小於其他架構。The mixed-signal design is a widely employed approach in communication IC design because it can benefit low hardware complexity and less chip-to-chip interfaces. The difficulties of mixed-signal design are often the interface components or signals between analog and digital circuits. These are many digital processing technologies to handle the interface signaling or controlling the analog components. We summarize these kinds of design/technology as the “Front-end Digital Signal Process” (Front-end DSP). In the thesis, we will define and discuss the designs of the Front-end DSP in both wireline and wireless communication systems. We firstly analyze the difficulties and issues of Front-end DSP for wireline and wireless applications. For wireline communication, we study the automatic gain control (AGC) and the equalizer in the Front-end DSP. Traditional approaches of AGC involve estimating the average power or the peak amplitude over an extended period, which results in high hardware complexity and a time-consuming evaluation. Moreover, the accuracy of traditional approaches is seriously degraded by noise and intersymbol interference (ISI). In this thesis, we propose a joint AGC and equalization (Joint AGC-EQ) scheme, in which the digital control unit (DCU) circuitry comprises only one-tenth of the area of a traditional AGC and the output power of the variable-gain amplifier can reach the optimal peak-to-average power ratio under different ISI environments. In addition, we provide a closed-form analysis of the convergence of the scheme, which shows that the total convergence time of Joint AGC-EQ is only half that of traditional blind equalization. The scheme is already silicon-proven for the application of a Fast Ethernet transceiver using Faraday/UMC 0.18-μm cell libraries. Experiments have revealed that the bit error rate is much better than the 802.3u specification, and that the scheme passes the stringent Killer Pattern testing of the University of New Hampshire InterOperability Laboratory. For wireless communication system, we study the automatic gain control (AGC) and the paceket detector (PD) of the Front-end DSP in Multiband orthogonal frequency-division multiplexing (MB-OFDM) system. The MB-OFDM systems employ frequency-hopping technology to achieve the capabilities of multiple access and frequency diversity. However, they also complicate the PD and time-frequency code synchronization, in terms of the requirement for fast synchronization for the frequency hopping, the extremely low receiver sensitivity, and the high hardware complexity. In this part, we systematically analyze the differences between MB-OFDM and conventional OFDM systems, and then propose a band tracking PD (BT-PD) that can cope with a worse-case multipath channel SNR of –8.4 dB with a packet detection error rate of less than 10–5. We also propose several low-cost design schemes for the BT-PD, such as Walsh-Hadamard decomposition, buffered summation, and sign-bit-remaining methods. The estimated gate count of the resulting implemented BT-PD is less than half that of existing solutions. In summary, we study the key components in Front-end DSP of both wireline and wireless communication systems. These components are very crucial but seldom discussed in previous researches. Our systematic approaches of the Front-end DSP can achieve the goals of PAPR optimization, low hardware complexity and better performance in mixed-signal baseband IC design.List of Figures ………………………………………………………...ix List of Tables ………………………………………………………..xii Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Definition and purpose of the Front-end DSP 3 1.3 Challenges of the Front-end DSP 5 1.4 Research Approaches 7 1.5 Dissertation Organization 8 Chapter 2 Design Issues of the Front-end DSP in Wireline Application …………………………………………………………9 2.1 Design target of the Front-end DSP 9 2.2 Problems of Conventional AGC schemes 12 2.2.1 Disadvantages of power-based AGC: 13 2.2.2 Disadvantages of peak-based AGC: 16 Chapter 3 Joint AGC-Equalization algorithm for Wirelined Receiver Designs 17 3.1 Derivation of the Joint AGC-EQ algorithm 17 3.1.1 Basic Ideal 17 3.1.2 System description 18 3.1.3 Main assumptions 20 3.1.4 Algorithm derivation 22 3.2 Design procedure and parameter search 25 3.3 Convergence Analysis of the Joint AGC-EQ algorithm 28 3.3.1 Review of conventional blind equalization 28 3.3.2 Convergence analysis of Joint AGC-EQ 29 3.3.3 Convergence properties of main/ZF weight and the VGA 31 3.3.4 MSE convergence behavior 33 3.4 Graphical illustration of the convergence behavior of the Joint AGC-EQ scheme 35 3.5 Simulation results 37 Chapter 4 VLSI Implementation and experimental results of EQ-AGC algorithm 43 4.1 Quantization approach of the DCU in Joint AGC-EQ 43 4.2 Hardware implementation of the DCU in Joint AGC-EQ 45 4.3 Application of Joint AGC-EQ to Fast Ethernet 47 4.4 System architecture and hardware fabrication information 49 4.5 Experimental results 51 4.6 Summary 53 Chapter 5 Introduction to MB-OFDM and the Design Issues 54 5.1 Design target of the Front-end DSP in wireless communication system 54 5.2 Specification of the MB-OFDM 55 5.2.1 PLCP frame format [25] 55 5.2.2 TFC and Band Hopping [25]-[27] 56 5.2.3 The difference between MB-OFDM and traditional OFDM 58 5.3 MB-OFDM Design Issues in the Front-end DSP 62 5.3.1 Specification issues 62 5.3.2 Hardware implementation problems 64 Chapter 6 Band-Tracking Packet Detector in OFDM-based Ultra-WideBand Systems 66 6.1 General description of BT-PD algorithm 66 6.2 The PD of the BT-PD algorithm 68 6.2.1 Symbol combiner 68 6.2.2 Symbol detector 70 6.2.3 Run-time CLI 74 6.3 Performance degradation of the BT-PD from the CFO 75 6.4 PD-based Automatic Gain Control 77 6.4.1 Power Estimator 78 6.4.2 Gain Updating 79 Chapter 7 The PDPC and FHC of the proposed BT-PD 83 7.1 PDPC 83 7.1.1 Operation description and receiver events 83 7.1.2 Probabilities of the performance and the procedure-improved gains 86 7.1.3 Design of the PDPC by hypothesis testing 88 7.2 Frequency hopping control 89 Chapter 8 Simulation results and Performance analysis 92 8.1 Simulation environment and specification 92 8.2 Simulation of the BT-PD operation 93 8.3 Performance measures 94 8.4 Performance comparison 95 8.4.1 System performance of an existing solution 95 8.4.2 System performance of the proposed BT-PD 97 Chapter 9 Hardware implementation of the proposed BT-PD 100 9.1 Sign-bit remaining in preamble coefficients 101 9.2 W-H decomposition and matched-filter retiming method 102 9.3 Buffered summation to reduce the squaring circuit 104 9.4 PNCR method 104 9.5 Cost–performance comparison of the low-cost BT-PD 106 9.6 Summary 109 Chapter 10 Conclusions and future works 110 10.1 Principal Contributions 110 10.2 Future works 111 References ………………………………………………………11