FPGA implementation of JPEG encoder architectures for wireless networks

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JPEG encoder architectures for wireless networks

While an old standard, the JPEG is still effective and used in many applications. Its relative simplicity is a clear advantage against its newest counterparts, i.e. the JPEG2000 and the JPEG XR, in many low-power scenarios. Moreover, features embedded in the JPEG2000 and the JPEG XR, such as the scalability of the image stream, can be added to the main JPEG core, making an encoder useful for example in a video surveillance wireless network. Nevertheless, the peculiar requirements of wireless, low-power scenarios require a dedicated hardware design, and a careful choice of the hardware architecture. In this work we developed several JPEG encoder architectures with full real-time reconfigurability, support for the restart intervals and for a simple scalability mechanisms, the scan scheme. These features make the architectures suitable for the use in lowbandwidth, low-power wireless networks. The JPEG encoder architectures have been developed, evaluated and compared using a cycle-based SystemC model