Reliability Analysis of Radiation Tolerant Low Voltage CCCII Circuit For Space Applications

In this paper, the impact of radiation on the MOS devices is investigated on recently reported programmablesecond generation Current Controlled Conveyor (CCCII) wherein some updates are suggested to take Hot Carrier Injection, Bias Temperature Instability, and Time Dependent Dielectric Breakdown into account. As radiation is yet another important factor that causes change in threshold voltage, the transistors which are amenable to larger threshold shift and may lead to functional failure are identified first. Subsequently, three possibilities; uses of all thin oxide devices, all thick oxide devices, and mixed devices are being investigate and it is found that while using mixed devices, the circuit becomes functional at lower voltage without any effective increase in leakage current. Architecture is updated to enhance the performance of circuits under time-based ageing and radiation environment. The major challenge is to control dynamic leakage and radiative noise due to imposed radiation. All simulations are carried out using 28nm CMOS technology models in Cadence Virtuoso environment using ±1.0V supply voltage and results have been verified with post layout netlist. Proposed circuit can function at low voltage with the reduced degradation for 8 years at 25 °C consumes less area as compared to the existing CCCII circuit with 0.008 FIT value

Investigation of Scaling and Temperature Effects in Total Ionizing Dose (TID) Experiments in 65 nm CMOS

Ten-fold radiation levels are expected in the upgrade of the High-Luminosity Large Hadron Collider (HL-LHC) at CERN. Bulk silicon CMOS at 65 nm offers appreciable advantages among cost, performance, and resilience to high Total Ionizing Dose (TID). In the present paper, geometrical scaling of key analog design parameters of MOS transistors irradiated at high TID is investigated. Experiments are carried out for TID of 100, 200 and up to 500 Mrad(SiO2) and at −30°C, 0°C, and 25°C. We find that parameters are least degraded at −30°C. However, short-channel NMOSTs show a significant degradation of slope factor, which is more severe at 0°C than at 25°C. In contrast, the slope factor in short-channel PMOSTs shows lowest sensitivity to high TID

Investigation of scaling and temperature effects in total ionizing dose (TID) experiments in 65 nm CMOS

Summarization: Ten-fold radiation levels are expected in the upgrade of the High-Luminosity Large Hadron Collider (HL-LHC) at CERN. Bulk silicon CMOS at 65 nm offers appreciable advantages among cost, performance, and resilience to high Total Ionizing Dose (TID). In the present paper, geometrical scaling of key analog design parameters of MOS transistors irradiated at high TID is investigated. Experiments are carried out for TID of 100, 200 and up to 500 Mrad(SiO2) and at -30°C, 0°C, and 25°C. We find that parameters are least degraded at -30°C. However, short-channel NMOSTs show a significant degradation of slope factor, which is more severe at 0°C than at 25°C. In contrast, the slope factor in short-channel PMOSTs shows lowest sensitivity to high TID.Παρουσιάστηκε στο: 25th International Conference ""Mixed Design of Integrated Circuits and Systems"