Grade de Hanan din?mica

WithMoore?slaw,theconstructionoflarge-scalecomponentsusingintegratedcircuits, ie a very-large-scale integration (VLSI) becomes increasingly complex, for this are used tools that seek to build models for a VLSI. Therefore, the proposed work is the implementation of a dynamicHanangridwithlessthan O(n2) complexityfortoolsthatusetheRegenerinearSteiner Minimum Tree (RSMT) to search for circuit integration. In addition to the implementation of the dynamic Hanan grid, an application using minimal paths and a bibliographical review of its operation. The tool is validated by test cases provided by the International Conference On Computer Aided Design (ICCAD) 2017.Com a lei de Moore a constru??o de componentes de larga escala utilizando-se de circuitos integrados, ou seja, uma Very-large-scale integration (VLSI) se torna cada vez mais complexa, para isto s?o utilizadas ferramentas que buscam construir modelos para uma VLSI. Com isto, a proposta deste trabalho ? a implementa??o de uma grade de Hanan din?mica com complexidade de espa?o inferior a O(n2) em ferramentas que se utilizem da Rectilinear Steiner Minimum Tree (RSMT) que buscam a integra??o de circuitos. Tendo como contribui??o, al?m da implementa??o da grade de Hanan din?mica, uma aplica??o utilizando caminhos min?mos e uma revis?o bibliogr??ca do funcionamento da mesma. A ferramenta ? validada por casos de testes dados pelo International Conference On Computer Aided Design (ICCAD) 2017

PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model

In static timing analysis, clock-to-q delays of flip-flops are considered as constants. Setup times and hold times are characterized separately and also used as constants. The characterized delays, setup times and hold times, are ap- plied in timing analysis independently to verify the perfor- mance of circuits. In reality, however, clock-to-q delays of flip-flops depend on both setup and hold times. Instead of being constants, these delays change with respect to different setup/hold time combinations. Consequently, the simple ab- straction of setup/hold times and constant clock-to-q delays introduces inaccuracy in timing analysis. In this paper, we propose a holistic method to consider the relation between clock-to-q delays and setup/hold time combinations with a piecewise linear model. The result is more accurate than that of traditional timing analysis, and the incorporation of the interdependency between clock-to-q delays, setup times and hold times may also improve circuit performance.Comment: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 201

On Uniformly Sampling Traces of a Transition System (Extended Version)

A key problem in constrained random verification (CRV) concerns generation of input stimuli that result in good coverage of the system's runs in targeted corners of its behavior space. Existing CRV solutions however provide no formal guarantees on the distribution of the system's runs. In this paper, we take a first step towards solving this problem. We present an algorithm based on Algebraic Decision Diagrams for sampling bounded traces (i.e. sequences of states) of a sequential circuit with provable uniformity (or bias) guarantees, while satisfying given constraints. We have implemented our algorithm in a tool called TraceSampler. Extensive experiments show that TraceSampler outperforms alternative approaches that provide similar uniformity guarantees.Comment: Extended version of paper that will appear in proceedings of International Conference on Computer-Aided Design (ICCAD '20); changed wrong text color in sec 7; added 'extended version

DiCA: A Hardware-Software Co-Design for Differential Checkpointing in Intermittently Powered Devices

Intermittently powered devices rely on opportunistic energy-harvesting to function, leading to recurrent power interruptions. This paper introduces DiCA, a proposal for a hardware/software co-design to create differential check-points in intermittent devices. DiCA leverages an affordable hardware module that simplifies the check-pointing process, reducing the check-point generation time and energy consumption. This hardware module continuously monitors volatile memory, efficiently tracking modifications and determining optimal check-point times. To minimize energy waste, the module dynamically estimates the energy required to create and store the check-point based on tracked memory modifications, triggering the check-pointing routine optimally via a nonmaskable interrupt. Experimental results show the cost-effectiveness and energy efficiency of DiCA, enabling extended application activity cycles in intermittently powered embedded devices.Comment: 8 pages and 7 figures. To be published at IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 202