SpinLink: An interconnection system for the SpiNNaker biologically inspired multi-computer

SpiNNaker is a large-scale biologically-inspired multi-computer designed to model very heavily distributed problems, with the flagship application being the simulation of large neural networks. The project goal is to have one million processors included in a single machine, which consequently span many thousands of circuit boards. A computer of this scale imposes large communication requirements between these boards, and requires an extensible method of connecting to external equipment such as sensors, actuators and visualisation systems. This paper describes two systems that can address each of these problems.Firstly, SpinLink is a proposed method of connecting the SpiNNaker boards by using time-division multiplexing (TDM) to allow eight SpiNNaker links to run at maximum bandwidth between two boards. SpinLink will be deployed on Spartan-6 FPGAs and uses a locally generated clock that can be paused while the asynchronous links from SpiNNaker are sending data, thus ensuring a fast and glitch-free response. Secondly, SpiNNterceptor is a separate system, currently in the early stages of design, that will build upon SpinLink to address the important external I/O issues faced by SpiNNaker. Specifically, spare resources in the FPGAs will be used to implement the debugging and I/O interfacing features of SpiNNterceptor

Interconnection system for the SpiNNaker biologically inspired multi-computer

SpiNNaker is a large-scale multi-core computing engine designed to model heavily distributed fine-grain problems. The machine is constructed hierarchically: 1 monitor and 16 worker processors form a single node of a toroidal compute 'surface'. The six high-speed bi-directional links of each node are used for triangular edge connections that provide alternative routes around problematic links. The system itself is scalable from one node up to 216 resulting in a maximum of 220 worker processors. SpiNNaker is an isotropic homogeneous network of processors that deliberately includes no central overseer. A consequence of this isotropy is an absence of perimeter and hence no natural position for peripheral I/O connections. This study describes the practical techniques and details employed in two components of the system: (a) SpiNNlink is the proposed board-to-board interconnection system that multiplexes 48 separate 250 Mbps SpiNNaker links through six off-board connections without compromising the overall system bisection bandwidth, forms an isotropic metanetwork on top of SpiNNaker without requiring any cooperation from system software, and remains transparent to the SpiNNaker network; and (b) SpiNNterceptor is the proposed peripheral I/O subsystem developed as a layer on top of SpiNNlink that provides over 18 Gbps of minimally disruptive communication between SpiNNaker applications and externally connected equipment

A Practical Hardware Implementation of Systemic Computation

It is widely accepted that natural computation, such as brain computation, is far superior to typical computational approaches addressing tasks such as learning and parallel processing. As conventional silicon-based technologies are about to reach their physical limits, researchers have drawn inspiration from nature to found new computational paradigms. Such a newly-conceived paradigm is Systemic Computation (SC). SC is a bio-inspired model of computation. It incorporates natural characteristics and defines a massively parallel non-von Neumann computer architecture that can model natural systems efficiently. This thesis investigates the viability and utility of a Systemic Computation hardware implementation, since prior software-based approaches have proved inadequate in terms of performance and flexibility. This is achieved by addressing three main research challenges regarding the level of support for the natural properties of SC, the design of its implied architecture and methods to make the implementation practical and efficient. Various hardware-based approaches to Natural Computation are reviewed and their compatibility and suitability, with respect to the SC paradigm, is investigated. FPGAs are identified as the most appropriate implementation platform through critical evaluation and the first prototype Hardware Architecture of Systemic computation (HAoS) is presented. HAoS is a novel custom digital design, which takes advantage of the inbuilt parallelism of an FPGA and the highly efficient matching capability of a Ternary Content Addressable Memory. It provides basic processing capabilities in order to minimize time-demanding data transfers, while the optional use of a CPU provides high-level processing support. It is optimized and extended to a practical hardware platform accompanied by a software framework to provide an efficient SC programming solution. The suggested platform is evaluated using three bio-inspired models and analysis shows that it satisfies the research challenges and provides an effective solution in terms of efficiency versus flexibility trade-off