2,776 research outputs found
Interconnection Networks for Scalable Quantum Computers
We show that the problem of communication in a quantum computer reduces to
constructing reliable quantum channels by distributing high-fidelity EPR pairs.
We develop analytical models of the latency, bandwidth, error rate and resource
utilization of such channels, and show that 100s of qubits must be distributed
to accommodate a single data communication. Next, we show that a grid of
teleportation nodes forms a good substrate on which to distribute EPR pairs. We
also explore the control requirements for such a network. Finally, we propose a
specific routing architecture and simulate the communication patterns of the
Quantum Fourier Transform to demonstrate the impact of resource contention.Comment: To appear in International Symposium on Computer Architecture 2006
(ISCA 2006
Interconnect Fabrics for Multi-Core Quantum Processors: A Context Analysis
Quantum computing has revolutionized the field of computer science with its
extraordinary ability to handle classically intractable problems. To realize
its potential, however, quantum computers need to scale to millions of qubits,
a feat that will require addressing fascinating yet extremely challenging
interconnection problems. In this paper, we provide a context analysis of the
nascent quantum computing field from the perspective of communications, with
the aim of encouraging the on-chip networks community to contribute and pave
the way for truly scalable quantum computers in the decades to come.Comment: 6 pages, 4 figures; appearing in Proceedings of the IEEE/ACM NoCArc
202
Principles of Neuromorphic Photonics
In an age overrun with information, the ability to process reams of data has
become crucial. The demand for data will continue to grow as smart gadgets
multiply and become increasingly integrated into our daily lives.
Next-generation industries in artificial intelligence services and
high-performance computing are so far supported by microelectronic platforms.
These data-intensive enterprises rely on continual improvements in hardware.
Their prospects are running up against a stark reality: conventional
one-size-fits-all solutions offered by digital electronics can no longer
satisfy this need, as Moore's law (exponential hardware scaling),
interconnection density, and the von Neumann architecture reach their limits.
With its superior speed and reconfigurability, analog photonics can provide
some relief to these problems; however, complex applications of analog
photonics have remained largely unexplored due to the absence of a robust
photonic integration industry. Recently, the landscape for
commercially-manufacturable photonic chips has been changing rapidly and now
promises to achieve economies of scale previously enjoyed solely by
microelectronics.
The scientific community has set out to build bridges between the domains of
photonic device physics and neural networks, giving rise to the field of
\emph{neuromorphic photonics}. This article reviews the recent progress in
integrated neuromorphic photonics. We provide an overview of neuromorphic
computing, discuss the associated technology (microelectronic and photonic)
platforms and compare their metric performance. We discuss photonic neural
network approaches and challenges for integrated neuromorphic photonic
processors while providing an in-depth description of photonic neurons and a
candidate interconnection architecture. We conclude with a future outlook of
neuro-inspired photonic processing.Comment: 28 pages, 19 figure
Scalable Emulation of Sign-ProblemFree Hamiltonians with Room Temperature p-bits
The growing field of quantum computing is based on the concept of a q-bit
which is a delicate superposition of 0 and 1, requiring cryogenic temperatures
for its physical realization along with challenging coherent coupling
techniques for entangling them. By contrast, a probabilistic bit or a p-bit is
a robust classical entity that fluctuates between 0 and 1, and can be
implemented at room temperature using present-day technology. Here, we show
that a probabilistic coprocessor built out of room temperature p-bits can be
used to accelerate simulations of a special class of quantum many-body systems
that are sign-problemfree or stoquastic, leveraging the well-known
Suzuki-Trotter decomposition that maps a -dimensional quantum many body
Hamiltonian to a +1-dimensional classical Hamiltonian. This mapping allows
an efficient emulation of a quantum system by classical computers and is
commonly used in software to perform Quantum Monte Carlo (QMC) algorithms. By
contrast, we show that a compact, embedded MTJ-based coprocessor can serve as a
highly efficient hardware-accelerator for such QMC algorithms providing several
orders of magnitude improvement in speed compared to optimized CPU
implementations. Using realistic device-level SPICE simulations we demonstrate
that the correct quantum correlations can be obtained using a classical
p-circuit built with existing technology and operating at room temperature. The
proposed coprocessor can serve as a tool to study stoquastic quantum many-body
systems, overcoming challenges associated with physical quantum annealers.Comment: Fixed minor typos and expanded Appendi
Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package
The grand challenge of scaling up quantum computers requires a full-stack
architectural standpoint. In this position paper, we will present the vision of
a new generation of scalable quantum computing architectures featuring
distributed quantum cores (Qcores) interconnected via quantum-coherent qubit
state transfer links and orchestrated via an integrated wireless interconnect.Comment: 5 pages, 2 figures, accepted for presentation at the IEEE
International Symposium on Circuits and Systems (ISCAS) 202
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