Speech Processing Front-end in Low-power Hardware

The objective of this work is to develop analog integrated circuits to serve as low-power auditory front-ends in signal processing systems. An analog front-end can be used for feature-extraction to reduce the requirements of the digital back-end, or to detect and call attention to compelling characteristics of a signal while the back-end is in sleep mode. Such a front-end should be advantageous for speech recognition, noise suppression, auditory scene analysis, hearing prostheses, biological modeling, or hardware-based event detection.;This work presents a spectral decomposition system, which consists of a bandpass filter bank with sub-band magnitude detection. The bandpass filter is low-power and each channel can be individually programmed for different quality factors and passband gains. The novel magnitude detector has a 68 decibel dynamic range, excellent tracking capability, and consumes less than a microwatt of power. The system, which was fabricated in a 0.18 micron process, consists of a 16-channel filter bank and a variety of sub-band computational elements

Analog VLSI Circuits for Biosensors, Neural Signal Processing and Prosthetics

Stroke, spinal cord injury and neurodegenerative diseases such as ALS and Parkinson's debilitate their victims by suffocating, cleaving communication between, and/or poisoning entire populations of geographically correlated neurons. Although the damage associated with such injury or disease is typically irreversible, recent advances in implantable neural prosthetic devices offer hope for the restoration of lost sensory, cognitive and motor functions by remapping those functions onto healthy cortical regions. The research presented in this thesis is directed toward developing enabling technology for totally implantable neural prosthetics that could one day restore lost sensory, cognitive and motor function to the victims of debilitating neural injury or disease. There are three principal components to this work. First, novel integrated biosensors have been designed and implemented to transduce weak extra-cellular electrical potentials and optical signals from cells cultured directly on the surface of the sensor chips, as well as to manipulate cells on the surface of these chips. Second, a method of detecting and identifying stereotyped neural signals, or action potentials, has been mapped into silicon circuits which operate at very low power levels suitable for implantation. Third, as one small step towards the development of cognitive neural implants, a learning silicon synapse has been implemented and a neural network application demonstrated. The original contributions of this dissertation include: * A contact image sensor that adapts to background light intensity and can asynchronously detect statistically significant optical events in real-time; * Programmable electrode arrays for enhanced electrophysiological recording, for directing cellular growth, for site-specific in situ bio-functionalization, and for analyte and particulate collection; * Ultra-low power, programmable floating gate template matching circuits for the detection and classification of neural action potentials; * A two transistor synapse that exhibits spike timing dependent plasticity and can implement adaptive pattern classification and silicon learning

Configurable analog hardware for neuromorphic Bayesian inference and least-squares solutions

Sparse approximation is a Bayesian inference program with a wide number of signal processing applications, such as Compressed Sensing recovery used in medical imaging. Previous sparse coding implementations relied on digital algorithms whose power consumption and performance scale poorly with problem size, rendering them unsuitable for portable applications, and a bottleneck in high speed applications. A novel analog architecture, implementing the Locally Competitive Algorithm (LCA), was designed and programmed onto a Field Programmable Analog Arrays (FPAAs), using floating gate transistors to set the analog parameters. A network of 6 coefficients was demonstrated to converge to similar values as a digital sparse approximation algorithm, but with better power and performance scaling. A rate encoded spiking algorithm was then developed, which was shown to converge to similar values as the LCA. A second novel architecture was designed and programmed on an FPAA implementing the spiking version of the LCA with integrate and fire neurons. A network of 18 neurons converged on similar values as a digital sparse approximation algorithm, with even better performance and power efficiency than the non-spiking network. Novel algorithms were created to increase floating gate programming speed by more than two orders of magnitude, and reduce programming error from device mismatch. A new FPAA chip was designed and tested which allowed for rapid interfacing and additional improvements in accuracy. Finally, a neuromorphic chip was designed, containing 400 integrate and fire neurons, and capable of converging on a sparse approximation solution in 10 microseconds, over 1000 times faster than the best digital solution.Ph.D

Indirect programming of floating-gate transistors

Abstract—Floating-gate (FG) transistors are useful for precisely programming a large array of current sources. Present FG programming techniques require disconnection of the transistor from the rest of its circuit while it is being programmed. We present a new method of programming FG transistors that does not require this disconnection. In this indirect programming method, two transistors share a FG allowing one to exist directly in a circuit while the other is reserved for programming. Since the transistor does not need to be disconnected from the circuit to program it, the switch count is reduced, resulting in fewer parasitics and better overall performance. Additionally, the use of these indirectly programmed FG transistors allows a circuit to be tuned such that the effects of device mismatch are negated. Finally, the concept of run-time programming is introduced which allows a circuit to be recalibrated while it is still operating within its system. Index Terms—Analog programmability, electron tunneling, floating-gate (FG) nFET, FG programming, FG transistor, hot-electron injection, indirect programming. I