Network coding meets TCP

We propose a mechanism that incorporates network coding into TCP with only minor changes to the protocol stack, thereby allowing incremental deployment. In our scheme, the source transmits random linear combinations of packets currently in the congestion window. At the heart of our scheme is a new interpretation of ACKs - the sink acknowledges every degree of freedom (i.e., a linear combination that reveals one unit of new information) even if it does not reveal an original packet immediately. Such ACKs enable a TCP-like sliding-window approach to network coding. Our scheme has the nice property that packet losses are essentially masked from the congestion control algorithm. Our algorithm therefore reacts to packet drops in a smooth manner, resulting in a novel and effective approach for congestion control over networks involving lossy links such as wireless links. Our experiments show that our algorithm achieves higher throughput compared to TCP in the presence of lossy wireless links. We also establish the soundness and fairness properties of our algorithm.Comment: 9 pages, 9 figures, submitted to IEEE INFOCOM 200

Road-based routing in vehicular ad hoc networks

Vehicular ad hoc networks (VANETs) can provide scalable and cost-effective solutions for applications such as traffic safety, dynamic route planning, and context-aware advertisement using short-range wireless communication. To function properly, these applications require efficient routing protocols. However, existing mobile ad hoc network routing and forwarding approaches have limited performance in VANETs. This dissertation shows that routing protocols which account for VANET-specific characteristics in their designs, such as high density and constrained mobility, can provide good performance for a large spectrum of applications. This work proposes a novel class of routing protocols as well as three forwarding optimizations for VANETs. The Road-Based using Vehicular Traffic (RBVT) routing is a novel class of routing protocols for VANETs. RBVT protocols leverage real-time vehicular traffic information to create stable road-based paths consisting of successions of road intersections that have, with high probability, network connectivity among them. Evaluations of RBVT protocols working in conjunction with geographical forwarding show delivery rate increases as much as 40% and delay decreases as much as 85% when compared with existing protocols. Three optimizations are proposed to increase forwarding performance. First, one- hop geographical forwarding is improved using a distributed receiver-based election of next hops, which leads to as much as 3 times higher delivery rates in highly congested networks. Second, theoretical analysis and simulation results demonstrate that the delay in highly congested networks can be reduced by half by switching from traditional FIFO with Taildrop queuing to LIFO with Frontdrop queuing. Third, nodes can determine suitable times to transmit data across RBVT paths or proactively replace routes before they break using analytical models that accurately predict the expected road-based path durations in VANETs

Real-Time Scheduling for Time-Sensitive Networking: A Systematic Review and Experimental Study

Time-Sensitive Networking (TSN) has been recognized as one of the key enabling technologies for Industry 4.0 and has been deployed in many time- and mission-critical industrial applications, e.g., automotive and aerospace systems. Given the stringent real-time communication requirements raised by these applications, the Time-Aware Shaper (TAS) draws special attention among the many traffic shapers developed for TSN, due to its ability to achieve deterministic latency guarantees. Extensive efforts on the designs of scheduling methods for TAS shapers have been reported in recent years to improve the system schedulability, each with their own distinct focuses and concerns. However, these scheduling methods have yet to be thoroughly evaluated, especially through experimental comparisons, to provide a systematical understanding on their performance using different evaluation metrics in various application scenarios. In this paper, we fill this gap by presenting a comprehensive experimental study on the existing TAS-based scheduling methods for TSN. We first categorize the system models employed in these work along with their formulated problems, and outline the fundamental considerations in the designs of TAS-based scheduling methods. We then perform extensive evaluation on 16 representative solutions and compare their performance under both synthetic scenarios and real-life industrial use cases. Through these experimental studies, we identify the limitations of individual scheduling methods and highlight several important findings. This work will provide foundational knowledge for the future studies on TSN real-time scheduling problems, and serve as the performance benchmarking for scheduling method development in TSN.Comment: 22 pages, ac

ABC: A Simple Explicit Congestion Controller for Wireless Networks

We propose Accel-Brake Control (ABC), a simple and deployable explicit congestion control protocol for network paths with time-varying wireless links. ABC routers mark each packet with an "accelerate" or "brake", which causes senders to slightly increase or decrease their congestion windows. Routers use this feedback to quickly guide senders towards a desired target rate. ABC requires no changes to header formats or user devices, but achieves better performance than XCP. ABC is also incrementally deployable; it operates correctly when the bottleneck is a non-ABC router, and can coexist with non-ABC traffic sharing the same bottleneck link. We evaluate ABC using a Wi-Fi implementation and trace-driven emulation of cellular links. ABC achieves 30-40% higher throughput than Cubic+Codel for similar delays, and 2.2X lower delays than BBR on a Wi-Fi path. On cellular network paths, ABC achieves 50% higher throughput than Cubic+Codel

Analysis and Modeling of Advanced PIM Architecture Design Tradeoffs

A major trend in high performance computer architecture over the last two decades is the migration of memory in the form of high speed caches onto the microprocessor semiconductor die. Where temporal locality in the computation is high, caches prove very effective at hiding memory access latency and contention for communication resources. However where temporal locality is absent, caches may exhibit low hit rates resulting in poor operational efficiency. Vector computing exploiting pipelined arithmetic units and memory access address this challenge for certain forms of data access patterns, for example involving long contiguous data sets exhibiting high spatial locality. But for many advanced applications for science, technology, and national security at least some data access patterns are not consistent to the restricted forms well handled by either caches or vector processing. An important alternative is the reverse strategy; that of migrating logic in to the main memory (DRAM) and performing those operations directly on the data stored there. Processor in Memory (PIM) architecture has advanced to the point where it may fill this role and provide an important new mechanism for improving performance and efficiency of future supercomputers for a broad range of applications. One important project considering both the role of PIM in supercomputer architecture and the design of such PIM components is the Cray Cascade Project sponsored by the DARPA High Productivity Computing Program. Cascade is a Petaflops scale computer targeted for deployment at the end of the decade that merges the raw speed of an advanced custom vector architecture with the high memory bandwidth processing delivered by an innovative class of PIM architecture. The work represented here was performed under the Cascade project to explore critical design space issues that will determine the value of PIM in supercomputers and contribute to the optimization of its design. But this work also has strong relevance to hybrid systems comprising a combination of conventional microprocessors and advanced PIM based intelligent main memory