3 research outputs found
Effective power saving method by on-chip traffic compression in noc-based embedded systems
[EN] of components, relying on an efficient on-chip network (network-on-chip; NoC). As
the size of the system increases, NoC performance and power consumption become a
central issue.
In this project, we design compression strategies at the NoC level reducing the number of
transmitted flits and consequently the energy consumed. The provided mechanism relies
on the abundance of memory data blocks filled with zeros in the analysed applications,
thus easily compressible by using a zero-elimination strategy. We provide a hardware
implementation for both compression and decompression end points at a generic network
interface (NI). The mechanisms have been designed in isolated mode in order to make
them modular and easily adapted to any NI protocol. Results show the effectiveness of the
compression and decompression mechanisms and the low overhead they introduce. The
percentage of traffic reduced by the compression strategy (it is reduced by a factor of 3)
justifies the added resources.
This work reflects some parts of the main research directions we tackle in the wider PhD
framework. In particular, we propose a method for power efficient memory traffic
management. The work presented here represents the initial research directions in
simulation development, traffic pattern characterization and initial solutions development[ES] Con los avances de la tecnología, los sistemas en chip multiprocesador (MPSoC)
aumentan en número de componentes, apoyándose en una red en el chip (NoC) eficiente.
Según crece el tamaño de estos sistemas, la eficiencia de la red tanto temporal como
energética se convierte en una parte primordial.
En este proyecto diseñamos estrategias de compresión a nivel de red (en la NoC)
reduciendo el número de flits transmitidos y por tanto la energía consumida. El método
propuesto se basa en la abundancia de bloques de memoria con largas cadenas de ceros
que se detectaron en las aplicaciones analizadas. Esta abundancia de ceros facilita la
compresión mediante estrategias de eliminación de ceros. Ofrecemos una
implementación hardware tanto de la parte de compresión como de la de descompresión
sobre un interfaz de red (NI) genérico. Los mecanismos propuestos han sido diseñados de
forma aislada para hacerlos modulares y fácilmente adaptables a cualquier protocolo de
NI. Los resultados muestran la efectividad de los mecanismos de compresión y
descompresión y la escasa penalización que introducen. El porcentaje de tráfico reducido
mediante la estrategia de compresión (se reduce con un factor de 3) justifica los recursos
extra requeridos.
Este trabajo refleja parte de la línea de investigación global que se pretende abordar en el
marco más amplio de un doctorado. En particular proponemos un método de gestión del
tráfico de memoria energéticamente eficiente. El trabajo presentado aquí representa pues
una primera aproximación a la investigación realizando un desarrollo parcial del
simulador, caracterización de patrones de tráfico y el desarrollo de una solución parcialSoler Heredia, M. (2013). Effective power saving method by on-chip traffic compression in noc-based embedded systems. http://hdl.handle.net/10251/43774Archivo delegad
Test-Delivery Optimization in Manycore SOCs
We present two test-data delivery optimization algorithms
for system-on-chip (SOC) designs with hundreds of cores,
where a network-on-chip (NOC) is used as the interconnection
fabric. We first present an e ective algorithm based on a subsetsum
formulation to solve the test-delivery problem in NOCs
with arbitrary topology that use dedicated routing. We further
propose an algorithm for the important class of NOCs with grid
topology and XY routing. The proposed algorithm is the first to
co-optimize the number of access points, access-point locations,
pin distribution to access points, and assignment of cores to access
points for optimal test resource utilization of such NOCs. Testtime
minimization is modeled as an NOC partitioning problem
and solved with dynamic programming in polynomial time. Both
the proposed methods yield high-quality results and are scalable
to large SOCs with many cores. We present results on synthetic
grid topology NOC-based SOCs constructed using cores from
the ITC’02 benchmark, and demonstrate the scalability of our
approach for two SOCs of the future, one with nearly 1,000 cores
and the other with 1,600 cores. Test scheduling under power
constraints is also incorporated in the optimization framework
Improving the Test of NoC-Based SoCs with Help of Compression Schemes
International audienceRe-using the network in a NoC-based system as a test access mechanism is an attractive solution as pointed out by several authors. As a consequence, testing of NoC-based SoCs is becoming a new challenge for designers. However, the effectiveness of testing methods is highly dependent on the number of test interfaces with the tester. This paper proposes the use of a test data compression scheme to increase the number of test interfaces (thus increasing test parallelism) without increasing the number of required Automated Test Equipment (ATE) channels. We show that the combination of compression and NoC-based test scheduling allows a drastic reduction of the system test time at the expense of a very small area overhead