Модифицированный метод декодирования турбо-кодов

Предложен модифицированный метод декодирования турбо-кодов, особенностью которого является комбинация различных декодеров в турбо-декодере, что позволяет уменьшить сложность и время декодирования

Wilis: Architectural Modeling of Wireless Systems

The performance of a wireless system depends on the wireless channel as well as the algorithms used in the transceiver pipelines. Because physical phenomena affect transceiver pipelines in difficult to predict ways, detailed simulation of the entire transceiver system is needed to evaluate even a single processing block. Further, some protocol validations require simulation of rare events (say, 1 bit error in 109 bits), which means the protocol must simulate for a long enough time for such events to materialize. This requirement coupled with the heavy computation typical of most physical-layer processing, rules out pure software solutions. In this paper we describe WiLIS, an FPGA-based hybrid hardware-software system designed to facilitate the development of wireless protocols. We then use WiLIS to evaluate several microarchitectures for measuring very low bit-error rates (BER). We demonstrate, for the first time, that the recently proposed SoftPHY can be implemented efficiently in hardware

Trellises and Trellis-Based Decoding Algorithms for Linear Block Codes

In a coded communication system with equiprobable signaling, MLD minimizes the word error probability and delivers the most likely codeword associated with the corresponding received sequence. This decoding has two drawbacks. First, minimization of the word error probability is not equivalent to minimization of the bit error probability. Therefore, MLD becomes suboptimum with respect to the bit error probability. Second, MLD delivers a hard-decision estimate of the received sequence, so that information is lost between the input and output of the ML decoder. This information is important in coded schemes where the decoded sequence is further processed, such as concatenated coding schemes, multi-stage and iterative decoding schemes. In this chapter, we first present a decoding algorithm which both minimizes bit error probability, and provides the corresponding soft information at the output of the decoder. This algorithm is referred to as the MAP (maximum aposteriori probability) decoding algorithm

Low-complexity iterative soft detection for LDPC coded multi-relay channels

Next generation wireless communication applications require reliable transmission of data at high data rates and a guarantee of quality-of-service over wireless links. However, degradations inherent in wireless channels, such as multipath fading, shadowing, path loss, and noise lead to reduction in the communication capacity and range significantly. One way to combat these adverse limitations is to employ spatial diversity, which can be achieved, for example, by transmitting independent copies of the signal over relay nodes, resulting in improvements in the transmission rates, reliability, and the capacity of the channel under pre-mentioned detrimental effects. In addition to exploiting diversity, the capacity of the channel can be further increased by employing an error correction code such as low-density parity check (LDPC) codes and turbo codes, etc. Throughout this thesis, we consider LDPC coded full-duplex multi-relay channels using Estimate and Forward (EF) and Decode and Forward (DF) protocol. We focus on designing optimal and sub-optimal iterative soft detectors. Although the use of multirelaying improves the channel reliability, the performance of the system is degraded because of the interference caused by multiple received signals coming from all relay nodes. To reduce the effect of the interference, maximum a posteriori (MAP) detector can be employed. Unfortunately, the complexity of the MAP detector grows exponentially as the number of relays increases. In the literature, two computationally efficient sub-optimal detectors have been proposed based on Taylor expansion or Central Limit Theorem (CLT) assumption to alleviate this problem. However, we find out that the correlation between intrinsic and extrinsic information stemming from these suboptimal detectors is very high, and this correlation degrades the detector performance. To remedy that, in this thesis, we developed two new detectors: Soft Decorrelating Detection-Taylor (SODED-Taylor) and Soft Decorrelating Detection-CLT (SODEDCLT), which improves the performance of sub-optimal detectors about 0.8 dB - 1 dB

Highly-configurable FPGA-based platform for wireless network research

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 155-164).Over the past few years, researchers have developed many cross-layer wireless protocols to improve the performance of wireless networks. Experimental evaluations of these protocols require both high-speed simulations and real-time on-air experimentations. Unfortunately, radios implemented in pure software are usually inadequate for either because they are typically two to three orders of magnitude slower than commodity hardware. FPGA-based platforms provide much better speeds but are quite difficult to modify because of the way high-speed designs are typically implemented by trading modularity for performance. Experimenting with cross-layer protocols requires a flexible way to convey information beyond the data itself from lower to higher layers, and a way for higher layers to configure lower layers dynamically and within some latency bounds. One also needs to be able to modify a layer's processing pipeline without triggering a cascade of changes. In this thesis, we discuss an alternative approach to implement a high-performance yet configurable radio design on an FPGA platform that satisfies these requirements. We propose that all modules in the design must possess two important design properties, namely latency-insensitivity and datadriven control, which facilitate modular refinements. We have developed Airblue, an FPGA-based radio, that has all these properties and runs at speeds comparable to commodity hardware. Our baseline design is 802.11g compliant and is able to achieve reliable communication for bit rates up to 24 Mbps. We show in the thesis that we can implement SoftRate, a cross-layer rate adaptation protocol, by modifying only 5.6% of the source code (967 lines). We also show that our modular design approach allows us to abstract the details of the FPGA platform from the main design, thus making the design portable across multiple FPGA platforms. By taking advantage of this virtualization capability, we were able to turn Airblue into a high-speed hardware software co-simulator with simulation speed beyond 20 Mbps.by Man Cheuk Ng.Ph.D