Sub-graph based joint sparse graph for sparse code multiple access systems

Sparse code multiple access (SCMA) is a promising air interface candidate technique for next generation mobile networks, especially for massive machine type communications (mMTC). In this paper, we design a LDPC coded SCMA detector by combining the sparse graphs of LDPC and SCMA into one joint sparse graph (JSG). In our proposed scheme, SCMA sparse graph (SSG) defined by small size indicator matrix is utilized to construct the JSG, which is termed as sub-graph based joint sparse graph of SCMA (SG-JSG-SCMA). In this paper, we first study the binary-LDPC (B-LDPC) coded SGJSG- SCMA system. To combine the SCMA variable node (SVN) and LDPC variable node (LVN) into one joint variable node (JVN), a non-binary LDPC (NB-LDPC) coded SG-JSG-SCMA is also proposed. Furthermore, to reduce the complexity of NBLDPC coded SG-JSG-SCMA, a joint trellis representation (JTR) is introduced to represent the search space of NB-LDPC coded SG-JSG-SCMA. Based on JTR, a low complexity joint trellis based detection and decoding (JTDD) algorithm is proposed to reduce the computational complexity of NB-LDPC coded SGJSG- SCMA system. According to the simulation results, SG-JSGSCMA brings significant performance improvement compare to the conventional receiver using the disjoint approach, and it can also outperform a Turbo-structured receiver with comparable complexity. Moreover, the joint approach also has advantages in terms of processing latency compare to the Turbo approaches

Concatenated Turbo/LDPC codes for deep space communications: performance and implementation

Deep space communications require error correction codes able to reach extremely low bit-error-rates, possibly with a steep waterfall region and without error floor. Several schemes have been proposed in the literature to achieve these goals. Most of them rely on the concatenation of different codes that leads to high hardware implementation complexity and poor resource sharing. This work proposes a scheme based on the concatenation of non-custom LDPC and turbo codes that achieves excellent error correction performance. Moreover, since both LDPC and turbo codes can be decoded with the BCJR algorithm, our preliminary results show that an efficient hardware architecture with high resource reuse can be designe

Advanced channel coding for space mission telecommand links

We investigate and compare different options for updating the error correcting code currently used in space mission telecommand links. Taking as a reference the solutions recently emerged as the most promising ones, based on Low-Density Parity-Check codes, we explore the behavior of alternative schemes, based on parallel concatenated turbo codes and soft-decision decoded BCH codes. Our analysis shows that these further options can offer similar or even better performance.Comment: 5 pages, 7 figures, presented at IEEE VTC 2013 Fall, Las Vegas, USA, Sep. 2013 Proc. IEEE Vehicular Technology Conference (VTC 2013 Fall), ISBN 978-1-6185-9, Las Vegas, USA, Sep. 201

VLSI implementation of a multi-mode turbo/LDPC decoder architecture

Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel contributions of this paper are: i) tackling the reconfiguration issue introducing a formal and systematic treatment that, to the best of our knowledge, was not previously addressed; ii) proposing a reconfigurable NoCbased turbo/LDPC decoder architecture and showing that wide flexibility can be achieved with a small complexity overhead. Obtained results show that dynamic switching between most of considered communication standards is possible without pausing the decoding activity. Moreover, post-layout results show that tailoring the proposed architecture to the WiMAX standard leads to an area occupation of 2.75 mm2 and a power consumption of 101.5 mW in the worst case