Design of low-phase-noise and low-power current-controlled oscillators

Oscillators are widely employed in many electronic systems for signal generations, conversions, and detections. There are two categories of oscillators, voltage-controlled oscillators (VCOs) and current-controlled oscillators (ICOs). The development of device technology and the sensor systems lead to more and more applications of ICOs. Moreover, many of applications require ICOs to operate under very restricted conditions. The objective of the work presented in this thesis is to design ICO circuits that meet the requirements of wide frequency range, high sensitivity to the control signal, low phase noise, low power dissipation, and small circuit space. To this end, the work of the design starts with a latch-based oscillator that has a simple structure and wide frequency range, but very modest performance of phase accuracy. A method to reduce the phase noise by introducing a Slope-Enhancement-Block (SEB) is proposed. The SEB is used to make the voltage variation at the critical node in the circuit enhanced so that the short-circuits currents are reduced. This method can hence help not only to reduce the phase noise, but also the power dissipation. With this method, two ICO circuits have been designed. By means of Spectre simulations, the performances of the two ICOs have been evaluated. The results show that by introducing the SEB each consisting of two cascaded inverters into the minimum-sized latch-based ICO, the phase noise can be reduced by at lest 5dBc/Hz. Such a simple SEB also helps to reduce significantly the power dissipation, in particular, at the lower part of the frequency range. Compared with the existing oscillators having a similar frequency range, the designed ICOs have a better performance in terms of phase noise and the comparable power dissipation when they are made to operate at the same current level. The phase noise of the first designed ICO circuit, ICO_NA, is -114.7 dBc/Hz at the offset frequency of 1 MHz from the carrier of 916 MHz with the power dissipation of 26.05 mW. The phase noise of the second designed ICO circuit, ICO_NB, is -113.9 dBc/Hz at the offset of 1 MHz from 913 MHz with the power dissipation of 19.64 mW. Moreover, they require much smaller silicon space of only 3933 om

Improved 6.7GHz CMOS VCO Delay Cell With Up To Seven Octave Tuning Range

The choice facing most VCO and PLL designers in modern CMOS processes is whether to use LC oscillators with large area and low phase noise, or to use an inverter based all transistor solution with poor phase noise, but much smaller size. This paper makes significant progress in closing the gap in performance between the inverter based and LC approaches. A novel double feedback dual inverter delay cell is proposed that achieves a significantly wider tuning range than previously reported whilst maintaining excellent phase noise performance. A design methodology is presented that includes noise analysis relating transistor level dimensions to the predicted phase noise performance. Two 120nm 1.2V design examples demonstrate that VCOs based on the improved delay cell can reach frequencies in excess of 6.7GHz, and that tuning ranges of over 7 octaves can be achieved