Efficient 1D and circular symmetric 2D FIR filters with variable cutoff frequencies using the Farrow structure and multiplier-block

IEEE International Symposium on Circuits and Systems, Sydney, NSW, Australia, 6-9 May 2001This paper proposes new structures for realizing 1D and circular symmetric 2D FIR filters with variable cutoff frequencies. They are based on the interpolation of the impulse responses using the Farrow structure. The coefficients of the sub-filters in the Farrow structure are represented in sum-of-powers-of-two (SOPOT) coefficients, which can easily be implemented as simple shifts and additions. Furthermore, using the transposed form realization of the sub-filters, all the SOPOT coefficients can be implemented by a single multiplier-block exploiting the redundancy among the SOPOT coefficients. Several design examples are given to demonstrate the effectiveness and feasibility of the proposed approach.published_or_final_versio

Design Of Polynomial-based Filters For Continuously Variable Sample Rate Conversion With Applications In Synthetic Instrumentati

In this work, the design and application of Polynomial-Based Filters (PBF) for continuously variable Sample Rate Conversion (SRC) is studied. The major contributions of this work are summarized as follows. First, an explicit formula for the Fourier Transform of both a symmetrical and nonsymmetrical PBF impulse response with variable basis function coefficients is derived. In the literature only one explicit formula is given, and that for a symmetrical even length filter with fixed basis function coefficients. The frequency domain optimization of PBFs via linear programming has been proposed in the literature, however, the algorithm was not detailed nor were explicit formulas derived. In this contribution, a minimax optimization procedure is derived for the frequency domain optimization of a PBF with time-domain constraints. Explicit formulas are given for direct input to a linear programming routine. Additionally, accompanying Matlab code implementing this optimization in terms of the derived formulas is given in the appendix. In the literature, it has been pointed out that the frequency response of the Continuous-Time (CT) filter decays as frequency goes to infinity. It has also been observed that when implemented in SRC, the CT filter is sampled resulting in CT frequency response aliasing. Thus, for example, the stopband sidelobes of the Discrete-Time (DT) implementation rise above the CT designed level. Building on these observations, it is shown how the rolloff rate of the frequency response of a PBF can be adjusted by adding continuous derivatives to the impulse response. This is of great advantage, especially when the PBF is used for decimation as the aliasing band attenuation can be made to increase with frequency. It is shown how this technique can be used to dramatically reduce the effect of alias build up in the passband. In addition, it is shown that as the number of continuous derivatives of the PBF increases the resulting DT implementation more closely matches the Continuous-Time (CT) design. When implemented for SRC, samples from a PBF impulse response are computed by evaluating the polynomials using a so-called fractional interval, µ. In the literature, the effect of quantizing µ on the frequency response of the PBF has been studied. Formulas have been derived to determine the number of bits required to keep frequency response distortion below prescribed bounds. Elsewhere, a formula has been given to compute the number of bits required to represent µ to obtain a given SRC accuracy for rational factor SRC. In this contribution, it is shown how these two apparently competing requirements are quite independent. In fact, it is shown that the wordlength required for SRC accuracy need only be kept in the µ generator which is a single accumulator. The output of the µ generator may then be truncated prior to polynomial evaluation. This results in significant computational savings, as polynomial evaluation can require several multiplications and additions. Under the heading of applications, a new Wideband Digital Downconverter (WDDC) for Synthetic Instruments (SI) is introduced. DDCs first tune to a signal\u27s center frequency using a numerically controlled oscillator and mixer, and then zoom-in to the bandwidth of interest using SRC. The SRC is required to produce continuously variable output sample rates from a fixed input sample rate over a large range. Current implementations accomplish this using a pre-filter, an arbitrary factor resampler, and integer decimation filters. In this contribution, the SRC of the WDDC is simplified reducing the computational requirements to a factor of three or more. In addition to this, it is shown how this system can be used to develop a novel computationally efficient FFT-based spectrum analyzer with continuously variable frequency spans. Finally, after giving the theoretical foundation, a real Field Programmable Gate Array (FPGA) implementation of a novel Arbitrary Waveform Generator (AWG) is presented. The new approach uses a fixed Digital-to-Analog Converter (DAC) sample clock in combination with an arbitrary factor interpolator. Waveforms created at any sample rate are interpolated to the fixed DAC sample rate in real-time. As a result, the additional lower performance analog hardware required in current approaches, namely, multiple reconstruction filters and/or additional sample clocks, is avoided. Measured results are given confirming the performance of the system predicted by the theoretical design and simulation

On the design and efficient implementation of the Farrow structure

This letter proposes an efficient implementation of the Farrow structure using sum-of-powers-of-two (SOPOT) coefficients and multiplier-block (MB). In particular, a novel algorithm for designing the Farrow coefficients in SOPOT form is detailed. Using the SOPOT coefficient representation, coefficient multiplication can be implemented with limited number of shifts and additions. Using MB, the redundancy between multipliers can be fully exploited through the reuse of the intermediate results generated. Design examples show that the proposed method can greatly reduce the complexity of the Farrow structure while providing comparable phase and amplitude responses.published_or_final_versio

Design and multiplier-less realization of matched filters with variable fractional delay for software radio receivers

The 47th Midwest Symposium on Circuits and Systems Conference, Salt Lake City, Utah, USA, 25-28 July 2004This paper studies the design and multiplier-less realization of variable fractional delay matched filters (VFD-MFs), which provide matching filtering and variable fractional delay of the filter output. It offers greater flexibility and lower delay in symbol-timing adjustment than directly cascading a match filter with a fractional delayer. The design of VFD-MFs, which can be viewed as a variable digital filter (VDF) design problem subject to the matched filtering condition, is formulated as a second order cone programming (SOCP) problem with least square design criteria. The proposed VFD-MFs can be efficiently implemented using the Farrow structure. By employing sum-of-power-of-two (SOPOT) coefficients and the multiplier block (MB) technique, very efficient multiplier-less realization of the VFD-MF with low hardware complexity is obtained. A design example is given to demonstrate the effectiveness of the proposed approach.published_or_final_versio

An efficient design or fractional-delay digital FIR filters using the Farrow structure

Fractional-delay digital filter (FD-DF), implemented using the Farrow (1988) structure, is very attractive in providing online tuning delay of digital signals. This paper proposes a new method for the design of such Farrow-based FD-DF using sum-of-powers-of-two (SOPOT) coefficients. Using the SOPOT coefficient representation, coefficient multiplication can be implemented with limited number of shifts and additions. Design examples show that the proposed method can greatly reduce the design time and complexity of the Farrow structure while providing comparable phase and amplitude responses.published_or_final_versio

The design and multiplier-less realization of software radio receivers with reduced system delay

This paper studies the design and multiplier-less realization of a new software radio receiver (SRR) with reduced system delay. It employs low-delay finite-impulse response (FIR) and digital allpass filters to effectively reduce the system delay of the multistage decimators in SRRs. The optimal least-square and minimax designs of these low-delay FIR and allpass-based filters are formulated as a semidefinite programming (SDP) problem, which allows zero magnitude constraint at ω = π to be incorporated readily as additional linear matrix inequalities (LMIs). By implementing the sampling rate converter (SRC) using a variable digital filter (VDF) immediately after the integer decimators, the needs for an expensive programmable FIR filter in the traditional SRR is avoided. A new method for the optimal minimax design of this VDF-based SRC using SDP is also proposed and compared with traditional weight least squares method. Other implementation issues including the multiplier-less and digital signal processor (DSP) realizations of the SRR and the generation of the clock signal in the SRC are also studied. Design results show that the system delay and implementation complexities (especially in terms of high-speed variable multipliers) of the proposed architecture are considerably reduced as compared with conventional approaches. © 2004 IEEE.published_or_final_versio

A versatile iterative framework for the reconstruction of bandlimited signals from their nonuniform samples

In this paper, we study a versatile iterative framework for the reconstruction of uniform samples from nonuniform samples of bandlimited signals. Assuming the input signal is slightly oversampled, we first show that its uniform and nonuniform samples in the frequency band of interest can be expressed as a system of linear equations using fractional delay digital filters. Then we develop an iterative framework, which enables the development and convergence analysis of efficient iterative reconstruction algorithms. In particular, we study the Richardson iteration in detail to illustrate how the reconstruction problem can be solved iteratively, and show that the iterative method can be efficiently implemented using Farrow-based variable digital filters with few general-purpose multipliers. Under the proposed framework, we also present a completed and systematic convergence analysis to determine the convergence conditions. Simulation results show that the iterative method converges more rapidly and closer to the true solution (i.e. the uniform samples) than conventional iterative methods using truncation of sinc series. © 2010 The Author(s).published_or_final_versionSpringer Open Choice, 21 Feb 201