Implementation of AMBA AHB protocol using verilog HDL

Advanced Microcontroller Bus Architecture (AMBA) is a series of bus protocols provided by ARM. These include AHB, APB and ASB. AMBA provides an on-chip communication standard for these buses to be used in high performance microcontrollers. In this paper we have implemented the AMBA AHB (Advanced High-Performance Bus) which is used for high performance transfers among different modules of the microcontroller. AHB supports efficient connection of processor, on chip memory, DMA and off chip external memories. AMBA AHB system bus supports multiple bus masters and slaves. The design is implemented using Verilog HDL and simulated using ModelSim 6.4a. Synthesis for the design is done using Xilinx ISE 14.4

A Bandwidth Control Arbitration for SoC Interconnections Performing Applications With Task Dependencies

Current System-on-Chips (SoCs) execute applications with task dependency that compete for shared resources such as buses, memories, and accelerators. In such a structure, the arbitration policy becomes a critical part of the system to guarantee access and bandwidth suitable for the competing applications. Some strategies proposed in the literature to cope with these issues are Round-Robin, Weighted Round-Robin, Lottery, Time Division Access Multiplexing (TDMA), and combinations. However, a fine-grained bandwidth control arbitration policy is missing from the literature. We propose an innovative arbitration policy based on opportunistic access and a supervised utilization of the bus in terms of transmitted flits (transmission units) that settle the access and fine-grained control. In our proposal, every competing element has a budget. Opportunistic access grants the bus to request even if the component has spent all its flits. Supervised debt accounts a record for every transmitted flit when it has no flits to spend. Our proposal applies to interconnection systems such as buses, switches, and routers. The presented approach achieves deadlock-free behavior even with task dependency applications in the scenarios analyzed through cycle-accurate simulation models. The synergy between opportunistic and supervised debt techniques outperforms Lottery, TDMA, and Weighted Round-Robin in terms of bandwidth control in the experimental studies performed

Design of reconfigurable embedded systems using Software-defined on-Chip interconnect elements

El conjunto de aplicaciones que hoy en día se ejecutan en los elementos de procesamiento en el interior de un Sistema en Chip (System-on-Chip (SoC), en inglés) requieren que el sistema de interconexión que los conecta, les permita cumplir con los requerimientos de Calidad en el Servicio (Quality of Service (QoS), en inglés) que les fueron establecidos. Los actuales sistemas de interconexión deben ser flexibles, reconfigurables, escalables, reutilizables y fáciles de administrar. En este documento se presenta una solución para un sistema de interconexión tipo bus basado en el paradigma de Redes Definidas por Software (Software Defined Network (SDN), en inglés). El trabajo muestra la arquitectura general del sistema de interconexión y en él se demuestra que la arquitectura cumple con las características anteriormente mencionadas. El trabajo pone especial énfasis en la capa de infraestructura del sistema -hardware-. Además, se incluyen los elementos de la capa de sistema operativo de red y se establecen sus interrelaciones con las capas adyacentes. En este trabajo también se muestra una nueva política de arbitraje basada en presupuestos la cual permite el uso diferenciado del bus. La política muestra un mejor comportamiento cuando el sistema funciona en escenarios ejecutando aplicaciones con tareas dependientes, los cuales son muy comunes en la actualidad. El sistema fue modelado en SystemC con precisión de ciclo de reloj. Las contribuciones realizadas en este trabajo pueden ser extrapoladas a otros sistemas de interconexión en SoC debido a que los retos que comparten son similares.The set of applications that today run in the processing elements inside a Systemon- Chip (SoC) require that the SoC interconnection system allows them to meet the Quality of Service (QoS) requirements that were established. Current interconnection systems must be exible, recon_gurable, scalable, reusable and easy to manage. This document presents a solution for a bus type interconnection system, based on the Software De_ned Network (SDN) paradigm. The work shows the general architecture of the interconnection system and demonstrates that this architecture meets the characteristics mentioned above. The work puts special emphasis on the infrastructure layer of the system | hardware |. However, it also establishes the elements to be included in the network operating system layer and its interrelation with the adjacent layers. This work also shows a new arbitration policy based on budgets that allows the di_erentiated use of the bus.The policy presents the best behavior when the system works in scenarios with applications executing dependent tasks, which are very common nowadays. The system was modeled in SystemC with clock cycle accuracy. The contributions made in this work can be extrapolated to other SoC interconnection systems because the challenges they share are similar