Implementation of LDPC encoding to DTMB standard based on FPGA

Conference Name:2011 10th IEEE/ACIS International Conference on Computer and Information Science, ICIS 2011. Conference Address: Sanya, Hainan Island, China. Time:May 16, 2011 - May 18, 2011.IEEE Computer Society; Int. Assoc. Comput. Inf. Sci. (ACIS); Institute of Electrical and Electronics Engineers (IEEE); Hainan UniversityIn this paper, an implementation of Low-Density Parity-Check (LDPC) encoder is introduced, which meets the demand of Chinese Digital Terrestrial Multimedia Broadcasting (DTMB) standard. A design of the LDPC encoder which uses a partially-parallel encoding structure based on the Shift Register Adder Accumulator (SRAA) circuit is studied according to the irregular quasi-cyclic characteristic of LDPC encoding specified by the standard. Then we use the FPGA to implement the design. The simulation and implementation results show that the design meets the requirement of DTMB standard and reduces the resource usage. ? 2011 IEEE