Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube

Memories that exploit three-dimensional (3D)-stacking technology, which integrate memory and logic dies in a single stack, are becoming popular. These memories, such as Hybrid Memory Cube (HMC), utilize a network-on-chip (NoC) design for connecting their internal structural organizations. This novel usage of NoC, in addition to aiding processing-in-memory capabilities, enables numerous benefits such as high bandwidth and memory-level parallelism. However, the implications of NoCs on the characteristics of 3D-stacked memories in terms of memory access latency and bandwidth have not been fully explored. This paper addresses this knowledge gap by (i) characterizing an HMC prototype on the AC-510 accelerator board and revealing its access latency behaviors, and (ii) by investigating the implications of such behaviors on system and software designs

FPGA Based Data Read-Out System of the Belle 2 Pixel Detector

The upgrades of the Belle experiment and the KEKB accelerator aim to increase the data set of the experiment by the factor 50. This will be achieved by increasing the luminosity of the accelerator which requires a significant upgrade of the detector. A new pixel detector based on DEPFET technology will be installed to handle the increased reaction rate and provide better vertex resolution. One of the features of the DEPFET detector is a long integration time of 20 {\mu}s, which increases detector occupancy up to 3 %. The detector will generate about 2 GB/s of data. An FPGA-based two-level read-out system, the Data Handling Hybrid, was developed for the Belle 2 pixel detector. The system consists of 40 read-out and 8 controller modules. All modules are built in {\mu}TCA form factor using Xilinx Virtex-6 FPGA and can utilize up to 4 GB DDR3 RAM. The system was successfully tested in the beam test at DESY in January 2014. The functionality and the architecture of the Belle 2 Data Handling Hybrid system as well as the performance of the system during the beam test are presented in the paper.Comment: Transactions on Nuclear Science, Proceedings of the 19th Real Time Conference, Preprin

The AXIOM software layers

AXIOM project aims at developing a heterogeneous computing board (SMP-FPGA).The Software Layers developed at the AXIOM project are explained.OmpSs provides an easy way to execute heterogeneous codes in multiple cores. People and objects will soon share the same digital network for information exchange in a world named as the age of the cyber-physical systems. The general expectation is that people and systems will interact in real-time. This poses pressure onto systems design to support increasing demands on computational power, while keeping a low power envelop. Additionally, modular scaling and easy programmability are also important to ensure these systems to become widespread. The whole set of expectations impose scientific and technological challenges that need to be properly addressed.The AXIOM project (Agile, eXtensible, fast I/O Module) will research new hardware/software architectures for cyber-physical systems to meet such expectations. The technical approach aims at solving fundamental problems to enable easy programmability of heterogeneous multi-core multi-board systems. AXIOM proposes the use of the task-based OmpSs programming model, leveraging low-level communication interfaces provided by the hardware. Modular scalability will be possible thanks to a fast interconnect embedded into each module. To this aim, an innovative ARM and FPGA-based board will be designed, with enhanced capabilities for interfacing with the physical world. Its effectiveness will be demonstrated with key scenarios such as Smart Video-Surveillance and Smart Living/Home (domotics).Peer ReviewedPostprint (author's final draft

A Multi Antenna Receiver for Galileo SoL Applications

One of the main features of the Galileo Satellite Navigation System is integrity. To ensure a reliable and robust navigation for Safety of Life applications, like CAT III aircraft landings, new receiver technologies are indispensable. Therefore, the German Aerospace Centre originated the development of a complete safety-of-life Galileo receiver to demonstrate the capabilities of new digital beam-forming and signal-processing algorithms for the detection and mitigation of interference. To take full advantage of those algorithms a carefully designed analogue signal processing is needed. The development addresses several challenging questions in the field of antenna design, frontend development and digital signal processing. The paper will give an insight in the activity and will present latest results

Real time plasma disruptions detection in JET implemented with the ITMS platform using FPGA based IDAQ

The use of FPGAs in data acquisition cards for processing purposes allows an efficient real time pattern recognition algorithm implementation. Using 13 JETs database waveforms an algorithm for detecting incoming plasma disruptions has been implemented. This algorithm is written in MATLAB using floating point representation. In this work we show the methodology used to implement the real time version of the algorithm using Intelligent Data Acquisition Cards (IDAQ), DAQ devices with field programmable gate array (FPGA) for local processing. This methodology is based on the translation of the MATLAB code to LabVIEW and the final coding of specific pieces of code in LabVIEW for FPGA in fixed point format. The whole system for evaluating the real time disruption detection (RTDD) has been implemented using the Intelligent Test and Measurement System (ITMS) platform. ITMS offers distributed data acquisition, distribution and real time processing capabilities with advanced, but easy to use, software tools that simplify application development and system setup. The RTDD implementation uses a standard PXI/PXIe architecture. Two 8 channel analog output cards play JETs database signals, two 8 channel DAQ with FPGA acquire signals and computes a feature vector based in FFT analysis. Finally the vector acquired is used by the system CPU to execute a pattern recognition algorithm to estimate an incoming disruption