Mechanism of dynamic bias temperature instability in p- and nMOSFETs: The effect of pulse waveform

The waveform effect on dynamic bias temperature instability (BTI) is systematically studied for both p- and nMOSFETs with ultrathin SiON gate dielectrics by using a modified direct-current current-voltage method to monitor the stress-induced interface trap density. Interface traps are generated at the inversion gate bias (negative for pMOSFETs and positive for nMOSFETs) and are partially recovered at the zero or accumulation gate bias. Devices under high-frequency bipolar stress exhibit a significant frequency-dependent degradation enhancement. Approximate analytical expressions of the interface trap generation for devices under the static, unipolar, or bipolar stress are derived in the framework of conventional reaction-diffusion (R-D) model and with an assumption that additional interface traps (N*it) are generated in each cycle of the dynamic stress. The additional interface trap generation is proposed to originate from the transient trapped carriers in the states at and/or near the SiO2/Si interface upon the gate voltage reversal from the accumulation bias to the inversion bias quickly, which may accelerate dissociation of Si-H bonds at the beginning of the stressing phase in each cycle. Hence, N*it depends on the interface-state density, the voltage at the relaxation (i.e., accumulation) bias, and the transition time of the stress waveform (the fall time for pMOSFETs and the rise time for nMOSFETs). The observed dynamic BTI behaviors can be perfectly explained by this modified R-D model

Impacts of the recovery phenomena on the worst-case of damage in DC/AC stressed ultra-thin NO gate-oxide MOSFETs

International audiencePermanent damage induced by Channel Hot-Carrier (CHC) injections have been distinguished from the charge-discharge of near-interface traps in ultra-thin gate-oxide (1.6nm) MOSFETs. It is shown that usual DC accelerating techniques mostly devoted to CHC damage at large voltage conditions cannot be used alone for low supply voltage (VDD= 1V) MOSFETs. This arises from the charging of slow traps which induces a worst-case of damage which is relaxing in different ways depending on the discharging bias and cold phases. This is particularly more severe under hole injections in P-channel than under electron injections in N-Channel MOSFETs in relation to the smaller mobility of holes and to the gate-oxide nitridation which induces deep traps from the oxide valence band. The true effects of the distinct damage and relaxations are further analyzed using AC stresses which are required for the worst-case determination in advanced logic circuits. This is further evidenced by the determination of the effective quasi-static time factors dependent on the alternated damaging, discharging, and relaxing periods involved in ultra-thin gate-oxide MOSFETs operating at low voltage