Targeted cooling with CVD diamond and micro-channel to meet 3-D IC heat dissipation challenge

Thermal simulation of a stack consists of three IC layers bonded “face up” is performed. It is shown that by inserting electrically isolated thermal through silicon via (TTSV) having Cu core and CVD diamond as a liner shell that extends across the layers to substrate, significant temperature reduction up to (103K) 62% can be achieved which also reflected through almost 60% reduction in thermal resistivity. Additionally simple microchannel integration with IC 3 layer and allowed fluid flow through the channel show transient temperature reduction. TTSV is also shown to be effective in mitigating severe heat dissipation issue facing 3-D IC bonded “face down” and logic layer stacked on memory substrate

Stress analysis in 3D IC having Thermal Through Silicon Vias (TTSV)

TTSV is proposed for the removal of heat from between the IC layers as these TTSVs carries heat down to the sink. However, it may generate stress in Silicon. In the present paper, thermal-stress simulation of stack consists of three IC layers bonded face up is performed using finite element modeling tools. We also analyzed the stress generated in 3D IC containing TTSV. Further we proposed a method for lower stress around the TTSV. The method proposed decreases the Von Misses Stress by a value of 40Mpa on average considering all the IC layers. Thus by achieving this, functionality of the chip becomes more reliable