Low-Cost On-Chip Clock Jitter Measurement Scheme

In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution

Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems

In this paper, we analyze the impact of error correcting codes (ECCs) on simultaneously switching outputs (SSO) noise, for the case of a realistic bus of a high reliability system. First, we analyze the effect of different bus transitions on SSO noise. Then we show how different ECCs, requiring a different number of check bits, impact the SSO noise. We prove that Hamming codes cause less noise than the ECCs that have been proposed so far to reduce power consumption and crosstalk-induced delay. In particular, we show that the code requirements for crosstalk and power minimization in terms of switching activity of adjacent wires are opposite to those for SSO noise reduction. Our analysis has been performed considering realistic bus and power supply network models, both implemented using a standard 0.25 ?m CMOS technology

Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems

In this paper we analyze the impact of error correcting codes (ECCs) on simultaneously switching outputs (SSO) noise, for the case of a realistic bus of a high reliability system. First we analyze the effect of different bus transitions on SSO noise. Then we show how different ECCs, requiring a different number of check bits, impact the SSO noise. We prove that Hamming codes cause less noise than the ECCs that have been proposed so far to reduce power consumption and crosstalk-induced delay. In particular, we show that the code requirements for crosstalk and power minimization in terms of switching activity of adjacent wires are opposite to those for SSO noise reduction. Our analysis has been performed considering realistic bus and power supply network models, both implemented using a standard 0.25 μm CMOS technology

Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems [error correcting codes]

In this paper, we analyze the impact of error correcting codes (ECCs) on simultaneously switching outputs (SSO) noise, for the case of a realistic bus of a high reliability system. First, we analyze the effect of different bus transitions on SSO noise. Then we show how different ECCs, requiring a different number of check bits, impact the SSO noise. We prove that Hamming codes cause less noise than the ECCs that have been proposed so far to reduce power consumption and crosstalk-induced delay. In particular, we show that the code requirements for crosstalk and power minimization in terms of switching activity of adjacent wires are opposite to those for SSO noise reduction. Our analysis has been performed considering realistic bus and power supply network models, both implemented using a standard 0.25 ?m CMOS technology