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PhD Forum: Impact of CNNs Pooling Layer Implementation on FPGAs Accelerator Design
Proceeding
ICDSC 2019 Proceedings of the 13th International Conference on Distributed Smart Cameras
Article No. 28. Trento, Italy — September 09 - 11, 2019Convolutional Neural Networks have demonstrated their competence
in extracting information from data, especially in the field
of computer vision. Their computational complexity prompts for
hardware acceleration. The challenge in the design of hardware
accelerators for CNNs is providing a sustained throughput with low
power consumption, for what FPGAs have captured community
attention. In CNNs pooling layers are introduced to reduce model
spatial dimensions. This work explores the influence of pooling
layers modification in some state-of-the-art CNNs, namely AlexNet
and SqueezeNet. The objective is to optimize hardware resources
utilization without negative impact on inference accuracyPeer reviewe