Design and Implementation of a High Performance Network Processor with Dynamic Workload Management

Internet plays a crucial part in today\u27s world. Be it personal communication, business transactions or social networking, internet is used everywhere and hence the speed of the communication infrastructure plays an important role. As the number of users increase the network usage increases i.e., the network data rates ramped up from a few Mb/s to Gb/s in less than a decade. Hence the network infrastructure needed a major upgrade to be able to support such high data rates. Technological advancements have enabled the communication links like optical fibres to support these high bandwidths, but the processing speed at the nodes remained constant. This created a need for specialised devices for packet processing in order to match the increasing line rates which led to emergence of network processors. Network processors were both programmable and flexible. To support the growing number of internet applications, a single core network processor has transformed into a multi/many core network processor with multiple cores on a single chip rather than just one core. This improved the packet processing speeds and hence the performance of a network node. Multi-core network processors catered to the needs of a high bandwidth networks by exploiting the inherent packet-level parallelism in a network. But these processors still had intrinsic challenges like load balancing. In order to maximise throughput of these multi-core network processors, it is important to distribute the traffic evenly across all the cores. This thesis describes a multi-core network processor with dynamic workload management. A multi-core network processor, which performs multiple applications is designed to act as a test bed for an effective workload management algorithm. An effective workload management algorithm is designed in order to distribute the workload evenly across all the available cores and hence maximise the performance of the network processor. Runtime statistics of all the cores were collected and updated at run time to aid in deciding the application to be performed on a core to to enable even distribution of workload among the cores. Hence, when an overloading of a core is detected, the applications to be performed on the cores are re-assigned. For testing purposes, we built a flexible and a reusable platform on NetFPGA 10G board which uses a FPGA-based approach to prototyping network devices. The performance of the designed workload management algorithm is tested by measuring the throughput of the system for varying workloads

Open source traffic analyzer

Proper traffic analysis is crucial for the development of network systems, services and protocols. Traffic analysis equipment is often based on costly dedicated hardware, and uses proprietary software for traffic generation and analysis. The recent advances in open source packet processing, with the potential of generating and receiving packets using a regular Linux computer at 10 Gb/s speed, opens up very interesting possibilities in terms of implementing a traffic analysis system based on open-source Linux. The pktgen software package for Linux is a popular tool in the networking community for generating traffic loads for network experiments. Pktgen is a high-speed packet generator, running in the Linux kernel very close to the hardware, thereby making it possible to generate packets with very little processing overhead. The packet generation can be controlled through a user interface with respect to packet size, IP and MAC addresses, port numbers, inter-packet delay, and so on. Pktgen was originally designed with the main goal of generating packets at very high rate. However, when it comes to support for traffic analysis, pktgen has several limitations. One of the most important characteristics of a packet generator is the ability to generate traffic at a specified rate. Pktgen can only do this indirectly, by inserting delays between packets. Moreover, the timer granularity prevents precise control of the transmission rate, something which severely reduces pktgen's usefulness as an analysis tool. Furthermore, pktgen lacks support for receiveside analysis and statistics generation. This is a key issue in order to convert pktgen into a useful network analyser tool. In this paper, improvements to pktgen are proposed, designed, implemented and evaluated, with the goal of evolving pktgen into a complete and efficient network analysis tool. The rate control is significantly improved, increasing the resolution and improving the usability by making it possible to specify exactly the sending rate. A receive-side tool is designed and implemented with support for measurement of number of packets, throughput, inter-arrival time, jitter and latency. The design of the receiver takes advantage of SMP systems and new features on modern network cards, in particular support for multiple receive queues and CPU scheduling. This makes it possible to use multiple CPUs to parallelize the work, improving the overall capacity of the traffic analyser. A significant part of the work has been spent on investigating low-level details of Linux networking. From this work we draw some general conclusions related to high speed packet processing in SMP systems. In particular, we study how the packet processing capacity per CPU depends on the number of CPUs. This work consists of minimal set of kernel patches to pktgen

Paketverarbeitende Systeme – Algorithmen und Architekturen für hohe Verarbeitungsgeschwindigkeiten

Paketverarbeitende Systeme basieren auf zwei wichtigen Bereichen: der eigentlichen Paketverarbeitung und der Paketklassifizierung. Zur Optimierung der Paketverarbeitung wurde eine FPGA-basierte Architektur für funktionale Module entwickelt, auf deren Basis verschiedene Funktionen für den Einsatz im Teilnehmerzugangsnetzwerk realisiert wurden. Hash-basierte Klassifizierungsalgorithmen und –architekturen sind grundsätzlich für die Paketklassifizierung geeignet. Zur Optimierung dieser Klasse von Algorithmen wurde eine evolvierbare Hashfunktionsarchitektur entwickelt.Packet processing systems base on two important areas: ultimate packet and packet classification. For optimization of packet processing an FPGA-based architecture for functional modules has been developed. For application in Access Network, different functional modules have been developed. Hash-based classification algorithms and architectures are appropriate for fast packet classification. For optimization of this class of algorithms, an evolvable architecture for hash functions has been developed