A Comparative Study of Single- and Dual-Threshold Voltage SRAM Cells, Journal of Telecommunications and Information Technology, 2011, nr 4

In this paper, a comparison has been drawn between 5 transistor (5T), 6T and 7T SRAM cells. All the cells have been designed using both single-threshold (conventional) and dual-threshold (dual-Vt) voltage techniques. Their respective delays and power consumption have been calculated at 180 nm and 65 nm CMOS technology. With technology scaling, power consumption decreases by 80% to 90%, with some increase in write time because of the utilization of high-Vt transistors in write critical path. The results show that the read delay of 7T SRAM cell is 9% lesser than 5T SRAM cell and 29% lesser than 6T SRAM cell due to the lower resistance of the read access delay path. While read power of 5T SRAM cell is reduced by 10% and 24% as compared to 7T SRAM, 6T SRAM cell respectively. The write speed, however, is degraded by 1% to 3% with the 7T and 5T SRAM cells as compared to the 6T SRAM cells due to the utilization of single ended architecture. While write power of 5T SRAM cell is reduced by up to 40% and 67% as compared to 7T SRAM, 6T SRAM cell respectively

Comparative Analysis of Self-Controllable Voltage Level (SVL) and Stacking Power Gating Leakage Reduction Techniques Using in Sequential Logic Circuit at 45Nanometer Regime

Abstract Today leakage power has become an increasingly major issue in low power VLSI design. With the most important element of leakage, the sub-threshold current, exponentially increasing with decreasing device dimension, leakage commands associate ever increasing share in the processor power consumption. In this paper two techniques such as transistor stacking and self controllable voltage-level (SVL) circuit for reducing leakage power in sequential circuits are proposed. This work analysis the power and delay of three different types of D Flip-flops using pass transistors logic, transmission gates and gate diffusion input (GDI) cmos design style. All the circuit parameters are simulated with and without the application of leakage reduction techniques. All these proposed circuits are simulated with and without the application of leakage reduction techniques. The circuits are simulated using Cadence Virtuoso tool at 45nm technology for various parameter

An Energy-Flow Model for Self-Powered Routers and its Application for Energy-Aware Routing

Abstract—Self-powered wireless mesh networks have gained popularity as a cheap alternative for providing Internet access in many rural areas of the developed and, especially, the developing world. The quality of service that these networks deliver is often bounded by such rudimentary issues as the unavailability of electrical energy. Dependence on renewable energy sources and variable power consumption make it difficult to predict the available energy and provide guarantees on the communication performance. We develop an energy flow model that accounts for communication and energy harvesting equipment hardware specifications; high resolution, time varying weather information; and the complex interaction among them. To show the model’s practical benefits we introduce an energy-aware routing protocol, the Lifetime Pattern based Routing (LPR), specifically tailored for self-powered wireless networks. LPR’s routing decisions are based on the energy level estimations provided by our energy flow model. The initial results are promising, and show our protocol outperform the existing work in rural-area wireless network routing. I

A Practical Framework to Study Low-Power Scheduling Algorithms on Real-Time and Embedded Systems

With the advanced technology used to design VLSI (Very Large Scale Integration) circuits, low-power and energy-efficiency have played important roles for hardware and software implementation. Real-time scheduling is one of the fields that has attracted extensive attention to design low-power, embedded/real-time systems. The dynamic voltage scaling (DVS) and CPU shut-down are the two most popular techniques used to design the algorithms. In this paper, we firstly review the fundamental advances in the research of energy-efficient, real-time scheduling. Then, a unified framework with a real Intel PXA255 Xscale processor, namely real-energy, is designed, which can be used to measure the real performance of the algorithms. We conduct a case study to evaluate several classical algorithms by using the framework. The energy efficiency and the quantitative difference in their performance, as well as the practical issues found in the implementation of these algorithms are discussed. Our experiments show a gap between the theoretical and real results. Our framework not only gives researchers a tool to evaluate their system designs, but also helps them to bridge this gap in their future works