IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

\u3cp\u3eIEEE Std P1838 is the DFT standard-under-development for 3D test access into dies meant to be used in 3D multi-die stack assemblies. P1838 is the first DFT standard to include a flexible parallel port (FPP): An optional, scalable multi-bit ('parallel') test access mechanism, offering higher test access bandwidth compared to the mandatory one-bit ('serial') port. In this paper, we describe P1838's FPP and propose a formal FPP specification language based on Google's Protocol Buffers (PBs), that potentially could become part of the standard. For a realistic example FPP, we provide its formal specification. Finally, we report on a demonstrator software tool, developed by using PBs-generated data access routines, that converts an FPP specification into a corresponding Verilog netlist.\u3c/p\u3

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

IEEE Std P1838 is the DFT standard-under-development for 3D test access into dies meant to be used in 3D multi-die stack assemblies. P1838 is the first DFT standard to include a flexible parallel port (FPP): An optional, scalable multi-bit ('parallel') test access mechanism, offering higher test access bandwidth compared to the mandatory one-bit ('serial') port. In this paper, we describe P1838's FPP and propose a formal FPP specification language based on Google's Protocol Buffers (PBs), that potentially could become part of the standard. For a realistic example FPP, we provide its formal specification. Finally, we report on a demonstrator software tool, developed by using PBs-generated data access routines, that converts an FPP specification into a corresponding Verilog netlist