2,681 research outputs found
A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems
In this paper, we present a novel cache design based on Multi-Level Cell
Spin-Transfer Torque RAM (MLC STTRAM) that can dynamically adapt the set
capacity and associativity to use efficiently the full potential of MLC STTRAM.
We exploit the asymmetric nature of the MLC storage scheme to build cache lines
featuring heterogeneous performances, that is, half of the cache lines are
read-friendly, while the other is write-friendly. Furthermore, we propose to
opportunistically deactivate ways in underutilized sets to convert MLC to
Single-Level Cell (SLC) mode, which features overall better performance and
lifetime. Our ultimate goal is to build a cache architecture that combines the
capacity advantages of MLC and performance/energy advantages of SLC. Our
experiments show an improvement of 43% in total numbers of conflict misses, 27%
in memory access latency, 12% in system performance, and 26% in LLC access
energy, with a slight degradation in cache lifetime (about 7%) compared to an
SLC cache
Efficient Placement and Migration Policies for an STT-RAM based Hybrid L1 Cache for Intermittently Powered Systems
The number of battery-powered devices is rapidly increasing due to the
widespread use of IoT-enabled nodes in various fields. Energy harvesters, which
help to power embedded devices, are a feasible alternative to replacing
battery-powered devices. In a capacitor, the energy harvester stores enough
energy to power up the embedded device and compute the task. This type of
computation is referred to as intermittent computing. Energy harvesters are
unable to supply continuous power to embedded devices. All registers and cache
in conventional processors are volatile. We require a Non-Volatile Memory
(NVM)-based Non-Volatile Processor (NVP) that can store registers and cache
contents during a power failure.
NVM-based caches reduce system performance and consume more energy than
SRAM-based caches. This paper proposes Efficient Placement and Migration
policies for hybrid cache architecture that uses SRAM and STT-RAM at the first
level cache. The proposed architecture includes cache block placement and
migration policies to reduce the number of writes to STT-RAM. During a power
failure, the backup strategy identifies and migrates the critical blocks from
SRAM to STT-RAM. When compared to the baseline architecture, the proposed
architecture reduces STT-RAM writes from 63.35% to 35.93%, resulting in a
32.85% performance gain and a 23.42% reduction in energy consumption. Our
backup strategy reduces backup time by 34.46% when compared to the baseline
Implementing a hybrid SRAM / eDRAM NUCA architecture
In this paper, we propose a hybrid cache architecture that exploits the main features of both memory technologies, speed of SRAM and high density of eDRAM. We demonstrate, that due to the high locality found in emerging applications, a high percentage of data that enters to the on-chip last-level cache are not accessed again before they are replacedPreprin
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