Simulation study of vertically stacked lateral Si nanowires transistors for 5 nm CMOS applications

In this paper we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, we used drift-diffusion methodology with activated Poisson-Schrodinger quantum corrections to accurately capture the quantum confinement in the cross-section of the device. Ensemble Monte Carlo simulations are used to accurately evaluate the drive current capturing the complexity of the carrier transport in the NWTs. We compared the current flow in single, double, and triple vertically stacked lateral NWTs with and without contact resistance. The results presented here suggest a consistent link between channel strain and device performance. Furthermore, we propose a device structure for the 5nm CMOS technology node that meets the required industry scaling projection. We also consider the interplay between various sources of statistical variability and reliability in this work

Modelling and simulation study of NMOS Si nanowire transistors

Nanowire transistors (NWTs) represent a potential alternative to Silicon FinFET technology in the 5nm CMOS technology generation and beyond. Their gate length can be scaled beyond the limitations of FinFET gate length scaling to maintain superior off-state leakage current and performance thanks to better electrostatic control through the semiconductor nanowire channels by gate-all-around (GAA) architecture. Furthermore, it is possible to stack nanowires to enhance the drive current per footprint. Based on these considerations, vertically-stacked lateral NWTs have been included in the latest edition of the International Technology Roadmap for Semiconductors (ITRS) to allow for further performance enhancement and gate pitch scaling, which are key criteria of merit for the new CMOS technology generation. However, electrostatic confinement and the transport behaviour in these devices are more complex, especially in or beyond the 5nm CMOS technology generation. At the heart of this thesis is the model-based research of aggressively-scaled NWTs suitable for implementation in or beyond the 5nm CMOS technology generation, including their physical and operational limitations and intrinsic parameter fluctuations. The Ensemble Monte Carlo approach with Poisson-Schrödinger (PS) quantum corrections was adopted for the purpose of predictive performance evaluation of NWTs. The ratio of the major to the minor ellipsoidal cross-section axis (cross-sectional aspect ratio - AR) has been identified as a significant contributing factor in device performance. Until now, semiconductor industry players have carried out experimental research on NWTs with two different cross-sections: circular cylinder (or elliptical) NWTs and nanosheet (or nanoslab) NWTs. Each version has its own benefits and drawbacks; however, the key difference between these two versions is the cross-sectional AR. Several critical design questions, including the optimal NWT cross-sectional aspect ratio, remain unanswered. To answer these questions, the AR of a GAA NWT has been investigated in detail in this research maintaining the cross-sectional area constant. Signatures of isotropic charge distributions within Si NWTs were observed, exhibiting the same attributes as the golden ratio (Phi), the significance of which is well-known in the fields of art and architecture. To address the gap in the existing literature, which largely explores NWT scaling using single-channel simulation, thorough simulations of multiple channels vertically-stacked NWTs have been carried out with different cross-sectional shapes and channel lengths. Contact resistance, non-equilibrium transport and quantum confinement effects have been taken into account during the simulations in order to realistically access performance and scalability. Finally, the individual and combined effects of key statistical variability (SV) sources on threshold voltage (VT), subthreshold slope (SS), ON-current (Ion) and drain-induced barrier lowering (DIBL) have been simulated and discussed. The results indicate that the variability of NWTs is impacted by device architecture and dimensions, with a significant reduction in SV found in NWTs with optimal aspect ratios. Furthermore, a reduction in the variability of the threshold voltage has been observed in vertically-stacked NWTs due to the cancelling-out of variability in double and triple lateral channel NWTs

Inorganic micro/nanostructures-based high-performance flexible electronics for electronic skin application

Electronics in the future will be printed on diverse substrates, benefiting several emerging applications such as electronic skin (e-skin) for robotics/prosthetics, flexible displays, flexible/conformable biosensors, large area electronics, and implantable devices. For such applications, electronics based on inorganic micro/nanostructures (IMNSs) from high mobility materials such as single crystal silicon and compound semiconductors in the form of ultrathin chips, membranes, nanoribbons (NRs), nanowires (NWs) etc., offer promising high-performance solutions compared to conventional organic materials. This thesis presents an investigation of the various forms of IMNSs for high-performance electronics. Active components (from Silicon) and sensor components (from indium tin oxide (ITO), vanadium pentaoxide (V2O5), and zinc oxide (ZnO)) were realised based on the IMNS for application in artificial tactile skin for prosthetics/robotics. Inspired by human tactile sensing, a capacitive-piezoelectric tandem architecture was realised with indium tin oxide (ITO) on a flexible polymer sheet for achieving static (upto 0.25 kPa-1 sensitivity) and dynamic (2.28 kPa-1 sensitivity) tactile sensing. These passive tactile sensors were interfaced in extended gate mode with flexible high-performance metal oxide semiconductor field effect transistors (MOSFETs) fabricated through a scalable process. The developed process enabled wafer scale transfer of ultrathin chips (UTCs) of silicon with various devices (ultrathin chip resistive samples, metal oxide semiconductor (MOS) capacitors and n‐channel MOSFETs) on flexible substrates up to 4″ diameter. The devices were capable of bending upto 1.437 mm radius of curvature and exhibited surface mobility above 330 cm2/V-s, on-to-off current ratios above 4.32 decades, and a subthreshold slope above 0.98 V/decade, under various bending conditions. While UTCs are useful for realizing high-density high-performance micro-electronics on small areas, high-performance electronics on large area flexible substrates along with low-cost fabrication techniques are also important for realizing e-skin. In this regard, two other IMNS forms are investigated in this thesis, namely, NWs and NRs. The controlled selective source/drain doping needed to obtain transistors from such structure remains a bottleneck during post transfer printing. An attractive solution to address this challenge based on junctionless FETs (JLFETs), is investigated in this thesis via technology computer-aided design (TCAD) simulation and practical fabrication. The TCAD optimization implies a current of 3.36 mA for a 15 μm channel length, 40 μm channel width with an on-to-off ratio of 4.02x 107. Similar to the NRs, NWs are also suitable for realizing high performance e-skin. NWs of various sizes, distribution and length have been fabricated using various nano-patterning methods followed by metal assisted chemical etching (MACE). Synthesis of Si NWs of diameter as low as 10 nm and of aspect ratio more than 200:1 was achieved. Apart from Si NWs, V2O5 and ZnO NWs were also explored for sensor applications. Two approaches were investigated for printing NWs on flexible substrates namely (i) contact printing and (ii) large-area dielectrophoresis (DEP) assisted transfer printing. Both approaches were used to realize electronic layers with high NW density. The former approach resulted in 7 NWs/μm for bottom-up ZnO and 3 NWs/μm for top-down Si NWs while the latter approach resulted in 7 NWs/μm with simultaneous assembly on 30x30 electrode patterns in a 3 cm x 3 cm area. The contact-printing system was used to fabricate ZnO and Si NW-based ultraviolet (UV) photodetectors (PDs) with a Wheatstone bridge (WB) configuration. The assembled V2O5 NWs were used to realize temperature sensors with sensitivity of 0.03% /K. The sensor arrays are suitable for tactile e-skin application. While the above focuses on realizing conventional sensing and addressing elements for e-skin, processing of a large amount of data from e-skin has remained a challenge, especially in the case of large area skin. A Neural NW Field Effect Transistors (υ-NWFETs) based hardware-implementable neural network (HNN) approach for tactile data processing in e-skin is presented in the final part of this thesis. The concept is evaluated by interfacing with a fabricated kirigami-inspired e-skin. Apart from e-skin for prosthetics and robotics, the presented research will also be useful for obtaining high performance flexible circuits needed in many futuristic flexible electronics applications such as smart surgical tools, biosensors, implantable electronics/electroceuticals and flexible mobile phones