Rad Tolerant CMOS Image Sensor Based on Hole Collection 4T Pixel Pinned Photodiode

1.4μm pixel pitch CMOS Image sensors based on hole collection pinned photodiode (HPD) have been irradiated with 60Co source. The HPD sensors exhibit much lower dark current degradation than equivalent commercial sensors using an Electron collection Pinned Photodiode (EPD). This hardness improvement is mainly attributed to carrier accumulation near the interfaces induced by the generated positive charges in dielectrics. The pre-eminence of this image sensor based on hole collection pinned photodiode architectures in ionizing environments is demonstrated

Versatile stochastic dot product circuits based on nonvolatile memories for high performance neurocomputing and neurooptimization.

The key operation in stochastic neural networks, which have become the state-of-the-art approach for solving problems in machine learning, information theory, and statistics, is a stochastic dot-product. While there have been many demonstrations of dot-product circuits and, separately, of stochastic neurons, the efficient hardware implementation combining both functionalities is still missing. Here we report compact, fast, energy-efficient, and scalable stochastic dot-product circuits based on either passively integrated metal-oxide memristors or embedded floating-gate memories. The circuit's high performance is due to mixed-signal implementation, while the efficient stochastic operation is achieved by utilizing circuit's noise, intrinsic and/or extrinsic to the memory cell array. The dynamic scaling of weights, enabled by analog memory devices, allows for efficient realization of different annealing approaches to improve functionality. The proposed approach is experimentally verified for two representative applications, namely by implementing neural network for solving a four-node graph-partitioning problem, and a Boltzmann machine with 10-input and 8-hidden neurons

Engineering Nanowire n-MOSFETs at Lg < 8 nm

As metal-oxide-semiconductor field-effect transistors (MOSFET) channel lengths (Lg) are scaled to lengths shorter than Lg<8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at Lg<8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON state currents in ultra scaled nanowire MOSFETs.Comment: 6 pages, 7 figures, journa

Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs

The characteristic performance of n-type and p-type inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode, bulk Germanium FinFET device with 3-nm gate length (LG) are demonstrated by using 3-D quantum transport device simulation. The simulated bulk Ge FinFET device exhibits favorable short channel characteristics, including drain-induced barrier lowering (DIBL&lt;10mV/V), sub threshold slope (SS∼64mV/dec.). Electron density distributions in ON-state and OFF-state also show that the simulated devices have large ION/IOFF ratios. Homogenous source/drain doping is maintained and only the channel doping is varied among different operating modes. Also, a constant threshold voltage |VTH|∼0.31V is maintained. Moreover, the calculated quantum capacitance (CQ) values of the Ge nanowire emphasizes the importance of quantum confinement effects (QCE) on the performance of the ultra-scaled devices

(Invited) towards a vertical and damage free post-etch InGaAs fin profile: dry etch processing, sidewall damage assessment and mitigation options

Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins

Radiation effects on CMOS image sensors with sub-2µm pinned photodiodes

A group of four commercial sensors with pixel pitches below 2μm has been irradiated with 60Co source at several total ionizing dose levels related to space applications. A phenomenological approach is proposed through behavior analysis of multiple sensors embedding different technological choices (pitch, isolation or buried oxide). A complete characterization including dark current, activation energy and temporal noise analysis allows to discuss about a degradation scheme