Design and implementation of generalized topologies of time-interleaved variable bandpass Σ−Δ modulators

In this thesis, novel analog-to-digital and digital-to-analog generalized time-interleaved variable bandpass sigma-delta modulators are designed, analysed, evaluated and implemented that are suitable for high performance data conversion for a broad-spectrum of applications. These generalized time-interleaved variable bandpass sigma-delta modulators can perform noise-shaping for any centre frequency from DC to Nyquist. The proposed topologies are well-suited for Butterworth, Chebyshev, inverse-Chebyshev and elliptical filters, where designers have the flexibility of specifying the centre frequency, bandwidth as well as the passband and stopband attenuation parameters. The application of the time-interleaving approach, in combination with these bandpass loop-filters, not only overcomes the limitations that are associated with conventional and mid-band resonator-based bandpass sigma-delta modulators, but also offers an elegant means to increase the conversion bandwidth, thereby relaxing the need to use faster or higher-order sigma-delta modulators. A step-by-step design technique has been developed for the design of time-interleaved variable bandpass sigma-delta modulators. Using this technique, an assortment of lower- and higher-order single- and multi-path generalized A/D variable bandpass sigma-delta modulators were designed, evaluated and compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity for ideal and non-ideal topologies. Extensive behavioural-level simulations verified that one of the proposed topologies not only used fewer coefficients but also exhibited greater robustness to non-idealties. Furthermore, second-, fourth- and sixth-order single- and multi-path digital variable bandpass digital sigma-delta modulators are designed using this technique. The mathematical modelling and evaluation of tones caused by the finite wordlengths of these digital multi-path sigmadelta modulators, when excited by sinusoidal input signals, are also derived from first principles and verified using simulation and experimental results. The fourth-order digital variable-band sigma-delta modulator topologies are implemented in VHDL and synthesized on Xilinx® SpartanTM-3 Development Kit using fixed-point arithmetic. Circuit outputs were taken via RS232 connection provided on the FPGA board and evaluated using MATLAB routines developed by the author. These routines included the decimation process as well. The experiments undertaken by the author further validated the design methodology presented in the work. In addition, a novel tunable and reconfigurable second-order variable bandpass sigma-delta modulator has been designed and evaluated at the behavioural-level. This topology offers a flexible set of choices for designers and can operate either in single- or dual-mode enabling multi-band implementations on a single digital variable bandpass sigma-delta modulator. This work is also supported by a novel user-friendly design and evaluation tool that has been developed in MATLAB/Simulink that can speed-up the design, evaluation and comparison of analog and digital single-stage and time-interleaved variable bandpass sigma-delta modulators. This tool enables the user to specify the conversion type, topology, loop-filter type, path number and oversampling ratio

Novel switched-capacitor circuits for delta-sigma modulators

Oversampled delta-sigma modulation is one of the widely used A/D conversion techniques for narrow bandwidth signals. In this study several new lowpass and bandpass delta-sigma modulator architectures as well as novel pseudo-N-path integrators that can be used in implementing these architectures are proposed. By using multiplexing techniques the new lowpass delta-sigma modulator architectures exchange higher clock rates with hardware complexity. For a given oversampling ratio (OSR), the multiplexed first-order delta-sigma modulator achieves a higher resolution. Guaranteed stability is a very desirable feature of these structures. The multi-loop delta-sigma modulator architecture similarly reduces the number of integrators needed to achieve high-resolution conversion for a given OSR. To ensure stability a quantizer with (N+1) bits must be used, where N is the number of loops, or in other words, the order of the delta-sigma modulator. Digital correction or randomizing techniques can be used to eliminate the performance reduction due to digital-to-analog- (D/A) converter nonlinearity error [59], [64]. Bandpass delta-sigma modulators are useful for applications such as AM radio receivers, spectrum analyzers, and digital wireless systems. Using z --> -z[superscript N] or z --> z[superscript N] mapping, a low pass delta-sigma modulator can be transformed to a bandpass one. One of the methods to implement the loop filters in bandpass delta-sigma modulators is to use Pseudo-N-Path (PNP) switched-capacitor (SC) integrators. The advantage is that the center frequency occurs exactly at an integer division of the sampling frequency because of the number of physical paths. To achieve maximum resolution, integrators that do not suffer from clock feedthrough peaks are needed. The proposed differential and single-ended novel PNP integrators address this problem [76]. To keep the opamp specifications less stringent while achieving high resolution, these PNP integrators have been further improved with gain compensation techniques [53]

Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter

Conversion of analog signals to their digital equivalent earlier in a circuit’s topology facilitates faster and more efficient exploitation of the information contained within. Analog-to-digital converters (ADCs) form the link between the analog and digital realms. In high frequency circuits ADCs must often be implemented further downstream after several stages of down-conversion, or through the use of more expensive technologies such as Bi-polar Junction Transistors or Gallium Arsenide. This thesis presents a technique to utilize Complimentary Metal Oxide Semiconductor technology in a parallel time-interleaved architecture. This will reduce circuit complexity and allow the ADC to be placed further upstream reducing the need for large and expensive analog hardware. This thesis utilizes an architecture that allows for higher frequency input signals through the use of down-sampling, parallel processing, and recombination. This thesis will also present the use of sigma delta based modulation in order to increase the resolution of the digital output signal. Exploitation of oversampling and the resultant noise-shaping characteristics of the sigma delta modulator will enable the user to gain resolution without the increased cost of implementing more expensive ADC architectures such as Flash. This thesis also presents a flexible converter such that both the center frequency and resolution can be modified by manipulating inputs. Specifically, the input and output filters as well as the sampling frequency can be tuned such that the circuit will operate at a particular center frequency. Also, the circuit will have flexible resolution which can be controlled by the clock input. Proof of concept is accomplished with a Matlab® simulation followed by schematic implementation in Cadence®. The design is constructed using IBM® 0.13 µm technology with a rail voltage of 1.2 V. Results are evaluated through the calculation of the effective number of bits and the signal to noise ratio. Conclusions and guidance on future research are provided

Distributed multi-user MIMO transmission using real-time sigma-delta-over-fiber for next generation fronthaul interface

To achieve the massive device connectivity and high data rate demanded by 5G, wireless transmission with wider signal bandwidths and higher-order multiple-input multiple-output (MIMO) is inevitable. This work demonstrates a possible function split option for the next generation fronthaul interface (NGFI). The proof-of-concept downlink architecture consists of real-time sigma-delta modulated signal over fiber (SDoF) links in combination with distributed multi-user (MU) MIMO transmission. The setup is fully implemented using off-the-shelf and in-house developed components. A single SDoF link achieves an error vector magnitude (EVM) of 3.14% for a 163.84 MHz-bandwidth 256-QAM OFDM signal (958.64 Mbps) with a carrier frequency around 3.5 GHz transmitted over 100 m OM4 multi-mode fiber at 850 nm using a commercial QSFP module. The centralized architecture of the proposed setup introduces no frequency asynchronism among remote radio units. For most cases, the 2 x 2 MU-MIMO transmission has little performance degradation compared to SISO, 0.8 dB EVM degradation for 40.96 MHz-bandwidth signals and 1.4 dB for 163.84 MHz-bandwidth on average, implying that the wireless spectral efficiency almost doubles by exploiting spatial multiplexing. A 1.4 Gbps data rate (720 Mbps per user, 163.84 MHz-bandwidth, 64-QAM) is reached with an average EVM of 6.66%. The performance shows that this approach is feasible for the high-capacity hot-spot scenario

Force feedback linearization for higher-order electromechanical sigma-delta modulators.

Abstract A higher-order electromechanical sigma–delta modulator can greatly improve the signal-to-noise ratio compared with a second-order loop that only uses the sensing element as a loop filter. However, the electrostatic force feedback on the proof mass is inherently nonlinear, which will produce harmonics in the output spectrum and limits the total signal-to-noise and distortion ratio. High performance inertial sensors, which use sigma–delta modulators as a closed-loop control system, have strict requirements on the output signal distortion. In this paper, nonlinear effects from the force feedback and pick-off circuits are analysed and a strategy for force feedback linearization is put forward which can considerably improve the signal-to-noise and distortion ratio. A PCB prototype of a fifth-order electromechanical modulator with a bulk micromachined accelerometer was used to demonstrate the concept

Adaptive design of delta sigma modulators

In this thesis, a genetic algorithm based on differential evolution (DE) is used to generate delta sigma modulator (DSM) noise transfer functions (NTFs). These NTFs outperform those generated by an iterative approach described by Schreier and implemented in the delsig Matlab toolbox. Several lowpass and bandpass DSMs, as well as DSM\u27s designed specifically for and very low intermediate frequency (VLIF) receivers are designed using the algorithm developed in this thesis and compared to designs made using the delsig toolbox. The NTFs designed using the DE algorithm always have a higher dynamic range and signal to noise ratio than those designed using the delsig toolbox

Output Filter Aware Optimization of the Noise Shaping Properties of {\Delta}{\Sigma} Modulators via Semi-Definite Programming

The Noise Transfer Function (NTF) of {\Delta}{\Sigma} modulators is typically designed after the features of the input signal. We suggest that in many applications, and notably those involving D/D and D/A conversion or actuation, the NTF should instead be shaped after the properties of the output/reconstruction filter. To this aim, we propose a framework for optimal design based on the Kalman-Yakubovich-Popov (KYP) lemma and semi-definite programming. Some examples illustrate how in practical cases the proposed strategy can outperform more standard approaches.Comment: 14 pages, 18 figures, journal. Code accompanying the paper is available at http://pydsm.googlecode.co

Low power all-digital radio-over-fiber transmission for 28-GHz band using parallel electro-absorption modulators

We present a low-power all-digital radio-over-fiber transmitter for beyond 28-GHz using sigma-delta modulation, a 140mW NRZ driver and parallel electro-absorption modulators. 5.25Gb/s (2.625Gb/s) 64-QAM is transported over 10-km SSMF at 1560nm with 7.6% (5.2%) EVM