2 research outputs found
Rapid Prototyping and Exploration Environment for Generating C-to-Hardware-Compilers
There is today an ever-increasing demand for more computational power
coupled with a desire to minimize energy requirements. Hardware
accelerators currently appear to be the best solution to this problem.
While general purpose computation with GPUs seem to be
very successful in this area, they perform adequately only in those cases where the data
access patterns and utilized algorithms fit the underlying
architecture. ASICs on the other hand can yield even better results
in terms of performance and energy consumption, but are very
inflexible, as they are manufactured with an application specific
circuitry. Field Programmable Gate Arrays (FPGAs) represent a combination of approaches: With their application specific hardware they provide
high computational power while requiring, for many applications, less
energy than a CPU or a GPU. On the other hand they are far more
flexible than an ASIC due to their reconfigurability.
The only remaining problem is the programming of
the FPGAs, as they are far more difficult to program compared to
regular software. To allow common software developers, who have at
best very limited
knowledge in hardware design, to make use of these devices, tools were
developed that take a regular high level language and generate
hardware from it.
Among such tools, C-to-HDL compilers are a particularly wide-spread approach. These compilers attempt to translate common C code into a hardware description language from which a
datapath is generated. Most of these compilers have many
restrictions for the input and differ in their underlying generated
micro architecture, their scheduling method, their applied
optimizations, their execution model and even their target
hardware. Thus, a comparison of a certain aspect alone, like their
implemented scheduling method or their generated micro architecture,
is almost impossible, as they differ in so many other aspects.
This work provides a survey of the existing C-to-HDL compilers and
presents a new approach to evaluating and exploring
different micro architectures for dynamic scheduling used by such
compilers. From a mathematically formulated rule set the Triad
compiler generates a backend for the Scale compiler framework,
which then implements a hardware generation backend with described dynamic
scheduling.
While more than a factor of four slower than hardware from highly
optimized compilers, this environment allows easy comparison and
exploration of different rule sets and the micro architecture for the
dynamically scheduled datapaths generated from them. For demonstration
purposes a rule set modeling the COCOMA token flow model from
the COMRADE 2.0 compiler was implemented. Multiple variants of
it were explored: Savings of up to 11% of the required hardware
resources were possible
High-Level-Language Compilation for Reconfigurable Computers
The compiler COMRADE accepts full ANSI C and compiles it into hybrid hardware/software applications for execution on a reconfigurable adaptive computer system. After defining the model-of-computation underlying the flow, we describe the general compilation process as well as some specific techniques. These include path-based partitioning, module-generator based datapath and controller synthesis, as well as reconfiguration scheduling