High-Level Synthesis of Scalable Architectures for IIR Filters Using Multichip Modules

We present a new technique for the high-level synthesis of scalable 1 MCM-based architectures implementing infiniteimpulse response(IIR) filters. Our technique is based on the regular schedules, a class of parallel schedules for computing mth-order IIR filters. The simplicity of the regular schedules facilitates characterization of their inter-processor communications, which is generally difficult to express for parallel algorithms. The characterization of inter-processor communications of the regular schedules enables us to generate instruction-level behavior of the design that can be easily mapped onto MCMbased architectures. We illustrate this mapping of the regular schedules onto an MCM-based architecture by designing a special-purpose processor for the fifth-order elliptic wave filter. Our design yields a scalable performancemeasured in the filter's sample rate, which is not known to have been achieved by previously published designs. This work differs significantly from "trad..