Developing the knowledge-based human resources that support the implementation of the National Dual Training System (NDTS): evaluation of TVET teacher's competency at MARA Training Institutions

Development in the world of technical and vocational education and training (TVET) on an ongoing basis is a challenge to the profession of the TVET-teachers to maintain their performance. The ability of teachers to identify the competencies required by their profession is very critical to enable them to make improvements in teaching and learning. For a broader perspective the competency needs of the labour market have to be matched by those developed within the vocational learning processes. Consequently, this study has focused on developing and validating the new empirical based TVET-teacher competency profile and evaluating teacher’s competency. This study combines both quantitative and qualitative research methodology that was designed to answer all the research questions. The new empirical based competency profile development and TVET-teacher evaluation was based upon an instructional design model. In addition, a modified Delphi technique has also been adopted throughout the process. Initially, 98 elements of competencies were listed by expert panel and rated by TVET institutions as important. Then, analysis using manual and statistical procedure found that 112 elements of competencies have emerged from seventeen (17) clusters of competencies. Prior to that, using the preliminary TVET-teacher competency profile, the level of TVETteacher competencies was found to be Proficient and the finding of 112 elements of competencies with 17 clusters was finally used to develop the new empirical based competency profile for MARA TVET-teacher. Mean score analysis of teacher competencies found that there were gaps in teacher competencies between MARA institutions (IKM) and other TVET institutions, where MARA-teacher was significantly better than other TVET teacher. ANOVA and t-test analysis showed that there were significant differences between teacher competencies among all TVET institutions in Malaysia. On the other hand, the study showed that teacher’s age, grade and year of experience are not significant predictors for TVET-teacher competency. In the context of mastering the competency, the study also found that three competencies are classified as most difficult or challenging, twelve competencies are classified as should be improved, and eight competencies are classified as needed to be trained. Lastly, to make NDTS implementation a reality for MARA the new empirical based competency profile and the framework for career development and training pathway were established. This Framework would serve as a significant tool to develop the knowledge based human resources needed. This will ensure that TVET-teachers at MARA are trained to be knowledgeable, competent, and professional and become a pedagogical leader on an ongoing basis towards a world class TVET-education system

The Influence of ZnO Layer Thickness on the Performance and Electrical Bias Stress Instality in ZnO Thin Film Transistors

University of Buea supported the first author during the writing of this manuscript Open access articleThin Film Transistors (TFTs) are the active elements for future large area electronic applications, in which low cost, low temperature processes and optical transparency are required. Zinc oxide (ZnO) thin film transistors (TFTs) on SiO2/n+-Si substrate are fabricated with the channel thicknesses ranging from 20 nm to 60 nm. It is found that both the performance and gate bias stress related instabilities of the ZnO TFTs fabricated were influenced by the thickness of ZnO active channel layer. The effective mobility was found to improve with increasing ZnO thickness by up to an order in magnitude within the thickness range investigated (20 – 60 nm). However, thinner films were found to exhibit greater stability in threshold voltage and turn-on voltage shifts with respect to both positive and negative gate bias stress. It was also observed that both the turn on voltage (Von) and the threshold voltage (VT) decrease with increasing channel thickness. Moreover, the variations in subthreshold slope (S) with ZnO thickness as well as variations in VT and Von suggest a possible dependence of trap states in the ZnO on the ZnO thickness. This is further correlated by the dependence of VT and Von instabilities with gate bias stress

Dielectric breakdown II: Related projects at the University of Twente

In this paper an overview is given of the related activities in our group of the University of Twente. These are on thin film transistors with the inherent difficulty of making a gate dielectric at low temperature, on thin dielectrics for EEPROM devices with well-known requirements with respect to charge retention and endurance and, finally, on thin film diodes in displays with unexpected breakdown properties

Impact of dopant species on the interfacial trap density and mobility in amorphous In-X-Zn-O solution-processed thin-film transistors

Alloying of In/Zn oxides with various X atoms stabilizes the IXZO structures but generates electron traps in the compounds, degrading the electron mobility. To assess whether the latter is linked to the oxygen affinity or the ionic radius, of the X element, several IXZO samples are synthesized by the sol-gel process, with a large number (14) of X elements. The IXZOs are characterized by XPS, SIMS, DRX, and UV-spectroscopy and used for fabricating thin film transistors. Channel mobility and the interface defect density NST, extracted from the TFT electrical characteristics and low frequency noise, followed an increasing trend and the values of mobility and NST are linked by an exponential relation. The highest mobility (8.5 cm2/Vs) is obtained in In-Ga-Zn-O, and slightly lower value for Sb and Sn-doped IXZOs, with NST is about 2E12 cm2/eV, close to that of the In-Zn-O reference TFT. This is explained by a higher electronegativity of Ga, Sb, and Sn than Zn and In, their ionic radius values being close to that of In and Zn. Consequently, Ga, Sb, and Sn induce weaker perturbations of In-O and Zn-O sequences in the sol-gel process, than the X elements having lower electronegativity and different ionic radius. The TFTs with X = Ca, Al, Ni and Cu exhibited the lowest mobility and NST > 1E13 cm2/eV, most likely because of metallic or oxide clusters formation

An amorphous oxide semiconductor thin-film transistor route to oxide electronics

Amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) invented only one decade ago are now being commercialized for active-matrix liquid crystal display (AMLCD) backplane applications. They also appear to be well positioned for other flat-panel display applications such as active-matrix organic light-emitting diode (AMOLED) applications, electrophoretic displays, and transparent displays. The objectives of this contribution are to overview AOS materials design; assess indium gallium zinc oxide (IGZO) TFTs for AMLCD and AMOLED applications; identify several technical topics meriting future scrutiny before they can be confidently relied upon as providing a solid scientific foundation for underpinning AOS TFT technology; and briefly speculate on the future of AOS TFTs for display and non-display applications

Modeling and Applications of Hydrogenated Amorphous Silicon Thin Film Transistors

Very recently, the hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) has shown its important application as an on-board driver for large-area flat-panel liquid crystal displays. It is also highly desirable to have on-board TFT logic circuits adjacent to the TFT driver matrix and have them implemented in the same technology on the same substrate. This reduces the number of lead connections to the display and hence the cost, and increases the reliability of the display. The first area to be investigated is the modeling of ID vs. VD static output characteristics of the n-channel a-Si:H TFT. Second, ambipolar characteristics of the a-Si:H TFT are investigated and modeled. Thereby device models for CAD circuit simulation programs are made available for circuit design. Third, a novel CMOS-like inverter circuit is presented as an application of the ambipolar a-Si:H TFT, and its static characteristics are analytically modeled. The transient response of the TFT is also characterized and modeled in order to understand its device limitations and to quantify its speed. Finally, the dynamic characteristics of the ambipolar a-Si:H TFT inverter are investigated and modeled so that its switching speed can be predicted and the optimized inverter can be designed

Silicon Nitride Deposition, Chromium Corrosion Mechanisms and Source/Drain Parasitic Resistance in Amorphous Silicon Thin Film transistors

Hydrogenated amorphous silicon (a-Si:H) based thin film transistors (TFTs) are finding increased application as switching elements in active-matrix liquid crystal displays (AMLCDs). Extensive research has been focussed on optimizing fabrication conditions to improve materials quality and on reducing channel length to increase device speed. However, the basic physics and chemistry have not yet been fully understood. In addition, little attention has been paid to the significant effect of source/drain parasitics. The work described in this thesis is closely related to the speed and stability issues on the discrete device level. Specifically, the influence of gate nitride deposition and its NH3 plasma treatment has been studied. The competing effects of nitridation reaction and radiation damage were found to cause an interesting trade-off between the device stability and speed. Further effort was devoted to the analysis of an important TFT failure phenomenon. Both electrical and spectroscopic techniques were utilized for gate Cr corrosion studies. It was determined that the corrosion was largely promoted by the CF4 plasma exposure of Cr during the fabrication. Finally, new test structures were designed, fabricated and characterized to study the source/drain parasitic resistance

Electrical characterisation of simple a-Si:H and nc-Si devices on paper substrates deposited by hot wire chemical vapour deposition and printing techniques

Includes bibliographical references (leaves 68-72).In this work we report on the electrical transport properties of two classes of silicon: hydrogenated amorphous silicon (a-Si:H) obtained by hot wire chemical vapour deposition (HWCVD), and printed nanocrystalline silicon (nc-Si), both deposited on a flexible, lightweight substrate of 80 g m-2 wood-free paper. For different devices such as field effect transistors and n-i-p solar cells, electrical measurements will be discussed. A special emphasis is placed on field effect mobility and amplification factor measurements because these provide information about the quality of the material

플라즈마 화학 기상 증착법을 이용한 베리어 필름 합성과 디스플레이 응용

학위논문 (박사)-- 서울대학교 대학원 : 자연과학대학 화학부, 2019. 2. 홍병희.자발광형 디스플레이이며, 저전압 구동이 가능하고 얇은 두께로 제작이 가능하며 동작속도가 매우 빠를 뿐만 아니라 높은 해상도 구현이 가능한 OLED는 디스플레이에서 빠른 성장세를 보이고 있다. 최근 OLED의 가장 큰 관심 분야는 모바일용 디스플레이와 대면적 TV, 그리고 플렉시블 및 투명 디스플레이 구현이다. 디스플레이를 구동하기 위한 구동소자는 수동형(passive matrix)과 능동형(active matrix, AM)로 나뉘며, 수동형에 비하여 고화질, 낮은 소비 전력, 대형화에 유리한 능동형 디스플레이가 선호된다. 표시소자를 능동 구동하기 위해서는 각 화소마다 박막 트랜지스터(thin-film transistor, TFT)와 같은 스위칭 소자를 부착시켜야 한다. 능동형 구동소자의 경우 현재의 TFT-LCD나 AMOLED용 백플레인에 주로 사용되는 비정질 실리콘(a-Si), 저온 다결정 실리콘 (LTPS) 기술이 우선 개발되어 응용되고 있다. 최근에는 큰 밴드 갭을 가지는 비정질 산화물 반도체를 이용해 투명하면서 빠른 응답속도의 디스플레이 구동소자에 대한 연구가 활발히 진행되고 있다. 또한 배선의 RC Delay를 최소화 시켜야 하고, 파워소비량을 줄여야 하는 기술적인 문제가 있다. 디스플레이의 고해상도인 UHD (Ultra High Definition)의 backplane에서 고속 TFT 구현을 위하여 SD(Source-Drain) 메탈 배선 구현은 필수적인 요소이다. 본 연구에서는 SD 메탈 배선으로써 저저항 배선인 Copper 배선의 diffusion barrier 역할을 하는 Graphite 성장을 다루고 있다. 기존의 Graphene 합성은 기계적 및 화학적 박리 방법에는 대면적 패널 구현으로써 한계가 있다. 현재까지 대형 Size scale Graphene 시도는 전극으로써 Graphene 활용은 있지만, 이 구현은 Thermal CVD (900~1000℃)에서 Graphene 을 합성하고, Glass에 transfer 한 논문으로써 실제 대면적으로 만드는 공정 적용에는 한계가 있다. 이에 현재 많이 연구는 진행 중이고 있지만, PECVD (Plasma Enhanced Chemical Vapor Deposition)를 이용한 graphite 박막 합성은 대형 size, mass production을 가능하게 하며, 아직 mass production 적용을 위해 연구해야 할 점은 많지만, 저온 공정 Graphite 합성이 가능하다면, large scale device 구현에 한층 더 진보된 기술이 될 것임을 확신한다. 본 연구에서 Copper diffusion barrier 으로써의 역할을 검증하고, 증착 온도를 저온으로 합성함으로써 TEM 및 EDAX 분석으로 Graphite barrier 및 mass production의 가능성을 검증하였다. 본 연구의 직접적인 PECVD 합성 방법을 통해 대면적이 가능함을 제시함으로써 기존의 대면적 합성 문제점을 해결해 줄 수 있는 방안이 될 것이다. 또한 디스플레이의 TFT 특성도 기존의 Active material 인 a-Si TFT보다 훨씬 더 높은 고이동도 소자를 요구하며, 특히 투명 디스플레이의 적용 가능하며, 고이동도 특성을 균일하게 가질 수 있는 신규 TFT를 요구하게 되었다. 이에 대한 방안으로 산화물 TFT로써 ZnO (Zinc Oxide), IZO (Indium Zinc Oxide), a-IGZO (Amorphous Indium Gallium Zinc Oxide) 등의 재료가 연구되고 있다. 기존의 a-Si의 이동도 (<1cm2/V·S) 보다 높은 이동도를 가진 IGZO 재료는 투명한 소자로써 투명디스플레이에서도 활용이 가능하여, 응용성을 확대하고 있다. 본 연구에서는 투명디스플레이 에서도 활용이 가능하도록 a-IGZO를 substrate로 하는 Graphite 박막을 합성 방법을 제시하고, 대면적 구현으로써 그 응용성을 기대하고 있다. Graphite의 저온 합성 기술 개발은 기존 라인의 CVD 장비 교체 없이 단지 Graphene Gas 사용만으로 공정을 구현한다는 점이 cost 및 공정 단순화의 관점에서 많은 장점이 있다. 또한 고속 구동을 위하여 SD 배선으로 metal뿐 아니라 산화물 반도체로도 Graphite 합성의 catalyst로써 사용되어, 패널 구현을 가능하게 해준다는 관점에서 의미가 있다. 또한 Graphite 합성 기술을 thin film 박막을 만들어 다른 application 에서도 활용 가능함을 보여줌으로써 파급 효과가 크다고 판단된다. 다음 연구에서는 LCD 디스플레이에서 Backlight 사용이 필수적이다. Back light는 가시광선 영역 뿐 아니라 UV 파장영역도 포함하고 있으며, Active 재료인 a-IGZO 소자에서 TFT 특성의 불안정성의 문제를 가지고 있다. IGZO의 특성상 UV 파장대에서의 빛과의 반응으로 TFT 소자의 신뢰성 특성이 악화되는 문제점을 해결하고자 Barrier 박막을 사용이 필수적인 요소이다. 본 연구에서는 TFT의 신뢰성 및 안정성을 유지하기 위해서 Photo blocking barrier로써 SiGe (Silicon Germanium) 박막 재료 합성을 통하여 TFT 신뢰성의 특성 변화 없는 것을 연구하였다. 이전 SiGe 연구되어진 바로는 태양전지에서 P-I(intrinsic layer)-N형 구조에서 중간 삽입층에서 불순물이 첨가되지 않은 무첨가층 (Intrinsic layer)에서 SiGe 이 광흡수층으로 사용되어진 연구가 있었다. 본 연구에서는 TFT 소자에서 a-IGZO 가 광반응으로 인해 산소 결핍 (Oxygen Vacancy)을 막아 TFT 특성의 저하 효과를 막고자 SiGe의 광 차단 박막 형성을 통해 광반응으로 인한a-IGZO특성 변화가 되지 않도록 하였다. 또한 박막 형성 및 적층 구조에서 SiGe 와 IGZO의 박막 사이에 Capacitance 형성으로 전자의 charge가 IGZO 박막 계면에 누적되어, 트랜지스터 특성이 단락(short) 현상이 발생 하였으며, 이를 방지하기 위해 Buffer layer 의 두께 조절이 중요하였다. 이에 Buffer layer의 두께 최적화를 통해 하부에서 들어오는 빛에도 차단을 할 수 있는 Barrier 적층 구조를 만들어 TFT 소자의 신뢰성 개선됨을 보여주고자 하였다. 스마트 Window 및 냉장고에서 문을 열지 않고 내용물을 확인할 수 있는 투명 디스플레이 및 플렉시블 디스플레이 구현을 위해 여러 요소의 기술 연구가 진행되고 있으며, 이 구현을 위해 본 연구의 Barrier 박막 구현은 필수적인 요소로 응용성이 확대되어 활용됨을 기대해 본다.OLED is a self-emissive display can be driven at low voltage and manufactured in a thin layer. In addition, this display operates at a very high speed and emit a color that can be rapidly implemented. Recently, OLEDs main interest is mobile screen, large screen TV, flexible and transparent display. The driving device for display is classified to the passive matrix and active matrix. Active matrix is preferred because of higher resolution, lower energy consumption, and large size screen. To apply active matrix on display device, a switching device such as thin-film transistor (TFT) is attached to each pixel. For active driving devices, amorphous silicon (a-Si) and low-temperature polycrystalline silicon (LTPS) technologies are applied in current TFT –LCD or AMOLED back frame. Recently, there is an ongoing research on using amorphous oxide semiconductors with large bandgaps to research transparent and fast responsive display driving devices. Moreover, RC delay has a technical problem that must be minimized and reduce power consumption. Implementation of Source Drain (SD) is a metal wiring essential element for high-speed TFT execution in high-resolution UHD (Ultra High Definition) displays backplane. In this study, the graphite growth plays the role of diffusion barrier of copper wiring that has low resistance wiring with SD metal wiring. The chemical and mechanical stripping methods of conventional graphene synthesis application on large area panels is limited. Up to now, the large size graphene has been used as an electrode, but this implementation is limited to making the large-scale process by synthesizing graphene at thermal CVD (900~1000°C) and transferring it to the glass. Despite the fact, a lot of ongoing studies, graphites thin film synthesis using Plasma Enhanced Chemical Vapor Deposition (PECVD) enables large size and mass production. Furthermore, this area still requires more research on mass production. If low-temperature process for graphite synthesis is possible, this will become a more advanced technology for device implementation. In this study, the role of copper diffusion barrier was verified, and the possibility of graphite barrier and mass production was verified by TEM and EDAX analysis by synthesizing the deposition temperature at low temperature. In addition, this study suggests the large size display can be obtained through direct PECVD synthesis that will solve the existing problems of large size synthesis. The displays TFT characteristics also require a high mobility device that is much higher than the conventional active material a-Si TFT. In particular, a new TFT capable of applying a transparent display and uniformly having high mobility characteristics is required. Materials such as ZnO (Zinc Oxide), IZO (Indium Zinc Oxide) and IGZO (Indium Gallium Zinc Oxide) have been studied as oxide TFTs. IGZO materials with higher mobility than conventional a-Si mobility (<1 cm2 / V · s) are transparent devices and can be used in transparent displays, thus extending applicability. In this study, we propose a graphite synthesis based on IGZO to be applicable to transparent display and expect the application on large size displays. The low-temperature Graphite synthesis has many advantages in terms of cost and process simplification because it implements the process only by using Graphene gas without replacing existing CVD equipment. In addition, it can be used as a graphite synthesis catalyst not only for metal but also for the oxide semiconductor, to raise activation. Moreover, the graphite synthesis to make a thin film can be applied to other fields. In the next study, it is essential to use backlight in LCD display. The backlight not only includes the visible light but also the UV region, and has instability of TFT characteristics in the active material IGZO device. Due to IGZOs reaction to light in UV region, it is essential to use a barrier film in order to solve the reliability characteristics of the TFT device deterioration. To maintain the reliability and stability of the TFT, this study on reliability of the TFT was not changed by SiGe (Silicon Germanium) synthesis thin film as a photo blocking barrier. Based on previous research on SiGe has been used as the light absorbing layer in the intrinsic layer in which a P-I (intrinsic layer)-N type structure in a solar cell that is not doped with an impurity in an intermediate insertion layer. In this study, in order to prevent oxygen vacancy during a-IGZO photoreaction on TFT device, the formation of a light-shielding film of Si-Ge prevents oxygen deficiency. Capacitance formation between SiGe and IGZO thin film in the thin film formation and lamination structure accumulates electrons charge on the IGZO thin film interface. The characteristics of the transistor were short, and to prevent this shortness, it is important to control the thickness of the buffer layer. Therefore, this shows that the reliability of the TFT device is improved by making the barrier laminate structure that can block the light from the bottom through the optimization of the thickness of the buffer layer. There are various ongoing technological studies on transparent and flexible displays that to observe the contents without opening the door through the smart window and refrigerator. For this application, the thin film barrier is an essential element and expect to be implemented.Table of Contents Abstract.........................................................................1 Contents........................................................................6 List of Figures.................................................................9 List of Tables................................................................15 Chapter 1. Introduction................................................16 1.1. Graphene characteristics 1.2. Amorphous Si:H and LTPS TFT backplane technology in display 1.3. High performance amorphous In-Ga-Zn-O TFTs 1.4. Overview of PECVD system 1.5. References Chapter 2. Growth of thin graphite films for solid diffusion barriers .......................................................60 2.1. Large-scale transfer-free growth of thin graphite films at low temperature for solid diffusion barriers 2.1.1. Introduction 2.1.2. Experimental 2.1.3. Results and discussion 2.1.4. Conclusion 2.1.5. References Chapter 3. Growth of silicon germanium films for photo-blocking layers in industrial display.................99 3.1. Silicon germanium photo-blocking layers for a-IGZO based industrial display 3.1.1. Introduction 3.1.2. Experimental 3.1.3. Results and Discussion 3.1.4. Conclusion 3.1.5. References Abstract in Korean………………………………………130 Appendix……………………………………………………135Docto