КОНВЕЙЕРНАЯ АРХИТЕКТУРА ДЕКОДЕРА CABAC СТАНДАРТА Н.264/AVC ДЛЯ МОБИЛЬНЫХ ПРИЛОЖЕНИЙ

The paper describes a three-stage pipeline architecture implementation of the CABAC decoder for mobile applications, with image resolution up to 625SD. The decoder architecture is suggested for pipeline calculations with the decoding performance of one bin per clock cycle. The decoder is compatible with profiles high profile, high 10 profile and high 4:2:2 profile and supports regime MBAFF and 8×8 blocks. It is scalable both in the resolution and in the supported decoding tools described in standard H.264. A comparison of our implementation with implementations of a prototype CABAC decoder on FPGA from the company Xilinx is given.Описывается архитектура декодера CABAC для мобильных приложений c разрешением до 625SD с трехступенчатым конвейером, позволяющая обеспечить декодирование одного бина за такт. Декодер совместим с профилями high profile, high 10 profile, high 4:2:2 profile, поддерживает режим MBAFF и блоки 8 ? 8, а также масштабируем как по разрешению, так и по поддерживаемым инструментам декодирования, описанным в стандарте H.264. Выполняется сравнение с известными реализациями прототипа декодера CABAC на FPGA фирмы Xilinx

Application-Specific Cache and Prefetching for HEVC CABAC Decoding

Context-based Adaptive Binary Arithmetic Coding (CABAC) is the entropy coding module in the HEVC/H.265 video coding standard. As in its predecessor, H.264/AVC, CABAC is a well-known throughput bottleneck due to its strong data dependencies. Besides other optimizations, the replacement of the context model memory by a smaller cache has been proposed for hardware decoders, resulting in an improved clock frequency. However, the effect of potential cache misses has not been properly evaluated. This work fills the gap by performing an extensive evaluation of different cache configurations. Furthermore, it demonstrates that application-specific context model prefetching can effectively reduce the miss rate and increase the overall performance. The best results are achieved with two cache lines consisting of four or eight context models. The 2 × 8 cache allows a performance improvement of 13.2 percent to 16.7 percent compared to a non-cached decoder due to a 17 percent higher clock frequency and highly effective prefetching. The proposed HEVC/H.265 CABAC decoder allows the decoding of high-quality Full HD videos in real-time using few hardware resources on a low-power FPGA.EC/H2020/645500/EU/Improving European VoD Creative Industry with High Efficiency Video Delivery/Film26

System-on-Chip design of a high performance low power full hardware cabac encoder in H.264/AVC

Ph.DDOCTOR OF PHILOSOPH

Design and Implementation of Pipelined CABAC Decoder for H.264/AVC

新的H.264/AVC標準在大部分的影片解析度與流量下，與先前的標準比較提供高達50%的壓縮增益。然而，解碼器所需複雜度大約是MPEG-2與MPEG-4 Visual Simple Profile的四倍！一些H.264/AVC提供的主要工具必須為此負責，包含可變區塊大小、哈達碼轉換、RD-拉格蘭吉最佳化、B畫面、1/4精度位移向量、增加的搜尋區域和參考畫面，與當然的本論文主角—CABAC。內容可適應性二位算數編碼器 (CABAC) 是H.264/AVC中提供的其中一項熵編碼，與其他內容可適應性可變長度編碼比較，CABAC承擔25%~30%的存取頻率負擔，但輸出編碼流量大約可減少16%。本論文提供一高效能、全管線化、解決資料相依性的CABAC解碼器，並且運作高達200MHz，相較其他舊設計兩倍以上的效能。Context Adaptive Binary Arithmetic Coding (CABAC) is one of the two alterna-tive entropy coding method specified in H.264/AVC. Compared with other tech-niques like Context Adaptive Variable Length Coding (CAVLC), CABAC brings access frequency increase from 25% to 30% with bit rate reduction up to 16%. In this thesis, we propose a high-performance and full-pipelined CABAC decoder without data dependency. And it can run at 200 MHz and have twice throughput of the fastest one of the previous works.Chapter1 Introduction 1 1.1 Introduction of the H.264/AVC CABAC 2 1.2 Previous Works 3 1.2.1 A high performance CABAC decoding architecture 3 1.2.2 High speed decoding of context-based adaptive binary arithmetic codes using most probable symbol prediction 5 1.2.3 Optimizing the critical loop in the H.264/AVC CABAC decoder 6 1.2.4 High-Performance CABAC Engine for H.264/AVC High Definition Real-Time Decoding 7 1.2.5 High-Speed H.264/AVC CABAC Decoding 9 1.2.6 A Time and Storage Optimized Hardware Design for Context-Based Adaptive Binary Arithmetic Decoding in H.264/AVC 10 1.2.7 A High-Performance Hardwired CABAC Decoder 11 1.2.8 A high-performance VLSI architecture for CABAC decoding in H.264/AVC 12 Chapter2 Overview of the H.264/AVC CABAC Decoding Algorithm 14 2.1 Initialization Process 15 2.1.1 Context variables initialization 15 2.1.2 Arithmetic Decoding Engine Initialization 17 2.2 Binarization Process 18 2.2.1 Unary binarization process 20 2.2.2 Truncated Unary (TU) binarization process 20 2.2.3 Concatenated unary/kth order Exp-Golomb (UEGK) binarization process 21 2.2.4 Fixed-length (FL) binarization process 22 2.2.5 Binarization process for coded block pattern 23 2.2.6 Binarization process for mb_qp_delta 23 2.2.7 Binarization process for macroblock type and sub-macroblock type 24 2.3 Decoding Process 24 2.3.1 Binary Decision Decoding Mode 27 2.3.2 Bypass Decoding Mode 28 2.3.3 Before Termination Decoding Mode 29 Chapter3 Proposed VLSI Architecture of H.264/AVC CABAC Decoding System 31 3.1 Design Motivation 32 3.2 System Controller Unit 33 3.2.1 Functions of the System Controller Unit 33 3.2.2 Architecture of the System Controller Unit 35 3.3 Get Model Unit 42 3.3.1 Functions of the Get Model Unit 42 3.3.2 Architecture of the Get Model Unit 43 3.4 Model Predicting Unit 46 3.4.1 Functions of the Model Predicting Unit 46 3.4.2 Architecture of the Model Predicting Unit 46 3.5 Get LPS Unit 47 3.5.1 Functions of the Get LPS Unit 47 3.5.2 Architecture of the Get LPS Unit 48 3.6 MPS Calculation Unit 50 3.6.1 Functions of the MPS Calculation Unit 50 3.6.2 Architecture of the MPS Calculation Unit 51 3.7 Get Bin Unit 55 3.7.1 Functions of the Get Bin Unit 55 3.7.2 Architecture of the Get Bin Unit 56 Chapter4 Implementation Result Verification and Comparison 59 4.1 Chip Specification 60 4.2 The Design Flow and the Verification Strategy 61 Chapter5 Conclusion 68 Reference 6