4 research outputs found

    Design of 8 and 16 Bit LFSR with Maximum Length Feedback Polynomial & Its pipelined Structure Using Verilog HDL

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    This paper is mainly concerned with the design of random sequences using Linear Feedback Shift Register (LFSR). This pseudo sequences is mainly used for various communication purposes. The other application such as banking, cryptographic, encoder & decoder. For hardware prototype FPGA is used because of its flexibility to reconfigure design many times. LFSR is a shift register whose output random state depends upon feedback polynomial. But by using pipelined architecture we can reduce the timing of random pattern generated at output by reducing the critical path. It can count maximum 2n-1 states and produce pseudo-random number at the output. Finally, comparing the simple and pipelined architecture of 8 & 16-bit LFSR

    Applications of the Galois Model LFSR in Cryptography

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    The linear feedback shift-register is a widely used tool for generating cryptographic sequences. The properties of the Galois model discussed here offer many opportunities to improve the implementations that already exist. We explore the overall properties of the phases of the Galois model and conjecture a relation with modular Golomb rulers. This conjecture points to an efficient method for constructing non-linear filtering generators which fulfil Golic s design criteria in order to maximise protection against his inversion attack. We also produce a number of methods which can improve the rate of output of sequences by combining particular distinct phases of smaller elementary sequences
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