An Architecture for On board Frequency Domain Analysis of Launch Vehicle Vibration Signals

The dynamic properties of the airborne structures plays a crucial role in the stability of the vehicle during flight. Modal and spectral behaviour of the structures are simulated and analysed. Ground tests are carried out with environmental conditions close to the flight conditions, with some assumptions. Subsequently, based on the flight telemetered data, the on-board mission algorithm and the auto-pilot filter coefficients are fine tuned. An attempt is made in this paper to design a novel architecture for analysing the modal and spectral random vibration signals on-board the flight vehicle and to identify the dominant frequencies. Based on the analysed results, the mission mode algorithm and the filter coefficients can be fine tuned on-board for better effectiveness in control and providing more stability. Three types of windows viz. Hann, Hamming and Blackman-Harris are configured with a generalised equation using FIR filter structure. The overlapping of the input signal data for better inclusiveness of the real-time data is implemented with BRAM. The domain conversion of the data from time domain to frequency domain is carried out with FFT using Radix-2 BF architecture. The FFT output data are processed for calculating the power spectral density. The dominant frequency is identified using the array search method and Goldschmidt algorithm is utilised for the averaging of the PSDs for better precision. The proposed architecture is synthesised, implemented and tested with both Synthetic and doppler signal of 300 Hz spot frequency padded with Gaussian white noise. The results are highly satisfactory in identifying the spot frequency and generating the PSD array

High performance multiplierless serial pipelined VLSI architecture for real-valued FFT

This paper presents a high-performance multiplierless serial pipelined architecture for real-valued fast Fourier transform (FFT). A new data mapping scheme (DMS) is suggested for the proposed serial pipelined FFT architecture. The performance is enhanced by performing FFT computations in log- 2 N-1 stages followed by a select-store-feedback (SSF) stage, where N is the number of points in FFT. Further enhancement in performance is achieved by employing quarter-complex multiplierless unit made up of memory and combinational logic in every stage. The memory stores half number of partial products while the remaining partial products are taken care by external combinational logic. Compared with the best existing scheme, the proposed design reduces the computational workload on half-butterfly (H-BF) units by (2N-8). Application specific integrated circuit (ASIC) and field programmable gate array (FPGA) results show that the proposed design for 1024-point achieves 31.54% less area, 30.13% less power, 33.56% less area-delay product (ADP), 27.11% less sliced look-up tables (SLUTs) and 28.37% less flip-flops (FFs) as compared to the best existing scheme.</p