Heterogeneous Multi-ASIP and NoC Based Architecture for Adaptive Parallel TBICM-ID-SSD

International audienceNovel multi-ASIP and Network-on-Chip (NoC) based flexible architecture for parallel Iterative Demapping with Turbo Decoding using Signal Space Diversity (TBICM-ID-SSD) is presented in this paper. The proposed heterogeneous multi-ASIP architecture uses multiple instances of two types of Application- Specific Instruction-set Processor (ASIP): one dedicated for turbo decoding and the second for demodulation, besides Butterfly topology based NoCs. This architecture presents novel and outstanding levels of flexibility and scalability in the design of advanced iterative receivers. It supports modulation schemes from BPSK to 256-QAM for any mapping style and supports 8 state single and double binary turbo code used in 3GPPLTE, DVB-RCS and Wimax. FPGA prototyping results are presented and the extra hardware cost required to enable turbo demodulation is evaluated