Algorithm-Architecture Co-Design for Digital Front-Ends in Mobile Receivers

The methodology behind this work has been to use the concept of algorithm-hardware co-design to achieve efficient solutions related to the digital front-end in mobile receivers. It has been shown that, by looking at algorithms and hardware architectures together, more efficient solutions can be found; i.e., efficient with respect to some design measure. In this thesis the main focus have been placed on two such parameters; first reduced complexity algorithms to lower energy consumptions at limited performance degradation, secondly to handle the increasing number of wireless standards that preferably should run on the same hardware platform. To be able to perform this task it is crucial to understand both sides of the table, i.e., both algorithms and concepts for wireless communication as well as the implications arising on the hardware architecture. It is easier to handle the high complexity by separating those disciplines in a way of layered abstraction. However, this representation is imperfect, since many interconnected "details" belonging to different layers are lost in the attempt of handling the complexity. This results in poor implementations and the design of mobile terminals is no exception. Wireless communication standards are often designed based on mathematical algorithms with theoretical boundaries, with few considerations to actual implementation constraints such as, energy consumption, silicon area, etc. This thesis does not try to remove the layer abstraction model, given its undeniable advantages, but rather uses those cross-layer "details" that went missing during the abstraction. This is done in three manners: In the first part, the cross-layer optimization is carried out from the algorithm perspective. Important circuit design parameters, such as quantization are taken into consideration when designing the algorithm for OFDM symbol timing, CFO, and SNR estimation with a single bit, namely, the Sign-Bit. Proof-of-concept circuits were fabricated and showed high potential for low-end receivers. In the second part, the cross-layer optimization is accomplished from the opposite side, i.e., the hardware-architectural side. A SDR architecture is known for its flexibility and scalability over many applications. In this work a filtering application is mapped into software instructions in the SDR architecture in order to make filtering-specific modules redundant, and thus, save silicon area. In the third and last part, the optimization is done from an intermediate point within the algorithm-architecture spectrum. Here, a heterogeneous architecture with a combination of highly efficient and highly flexible modules is used to accomplish initial synchronization in at least two concurrent OFDM standards. A demonstrator was build capable of performing synchronization in any two standards, including LTE, WiFi, and DVB-H

Timing and Carrier Synchronization in Wireless Communication Systems: A Survey and Classification of Research in the Last 5 Years

Timing and carrier synchronization is a fundamental requirement for any wireless communication system to work properly. Timing synchronization is the process by which a receiver node determines the correct instants of time at which to sample the incoming signal. Carrier synchronization is the process by which a receiver adapts the frequency and phase of its local carrier oscillator with those of the received signal. In this paper, we survey the literature over the last 5 years (2010–2014) and present a comprehensive literature review and classification of the recent research progress in achieving timing and carrier synchronization in single-input single-output (SISO), multiple-input multiple-output (MIMO), cooperative relaying, and multiuser/multicell interference networks. Considering both single-carrier and multi-carrier communication systems, we survey and categorize the timing and carrier synchronization techniques proposed for the different communication systems focusing on the system model assumptions for synchronization, the synchronization challenges, and the state-of-the-art synchronization solutions and their limitations. Finally, we envision some future research directions

WIMAX INNER RECEIVER DESIGN

"Igniting broadband wireless access". That is the vision for WiMAX, which is defined in the 802.16 standards to cover the frequency bands within the 2 to 66 GHz region. It promises an OFDM air interface with data rates comparable to wireline services (cable and xDSL). Coupled with QoS provisioning and support for NLOS propagation, WiMAX offers the platform for real time multimedia communications in addition to being able to replace the existing legacy PSTN. WiMAX also becomes the perfect launch pad for service providers to roll out triple play. The standard based products and availability of internet to anyone, anywhere and anytime will almost guarantee the widespread adoption ofWiMAX everywhere. This FYP attempts to simulate the working mechanism of a WiMAX receiver, with focus on synchronization (inner receiver), via simulation in Simulink. The undertaking will involve the baseband physical radio link. The proposed method of synchronization is a novel hybrid of a modified version of the Schmidl and Cox technique and the double sliding window packet detection. The inner receiver deals with synchronization issues such as FFT timing offset and carrier frequency offset. Offsets and impairments are deliberately introduced into the system to ensure that the receiver is totally blind and to fully test the proposed algorithm. Results indicate that the proposed method can harness the best features of both worlds. Frame timing synchronization is achieved accurately without uncertainties of detecting a plateau. On the other hand, frequency offsets are dealt with efficiently using the tried and tested Schmidl and Cox technique. All in all, the proposed synchronization scheme is very well suited for WiMAX systems. The proposed method can achieve rapid synchronization with low overhead

A hybrid optical-wireless network for decimetre-level terrestrial positioning

Global navigation satellite systems (GNSS) are widely used for navigation and time distribution, features indispensable for critical infrastructure such as mobile communication networks, as well as emerging technologies like automated driving and sustainable energy grids. While GNSS can provide centimetre-level precision, GNSS receivers are prone to many-metre errors due to multipath propagation and obstructed view of the sky, which occur especially in urban areas where accurate positioning is needed most. Moreover, the vulnerabilities of GNSS, combined with the lack of a back-up system, pose a severe risk to GNSS-dependent technologies. Here, we demonstrate a terrestrial positioning system which is independent of GNSS and offers superior performance through a constellation of radio transmitters, connected and time-synchronised at the sub-nanosecond level through a fibre-optic Ethernet network. Employing optical and wireless transmission schemes similar to those encountered in mobile communication networks, and exploiting spectrally efficient virtual wideband signals, the detrimental effects of multipath propagation are mitigated, thus enabling robust decimetre-level positioning and sub-nanosecond timing in a multipath-prone outdoor environment. This work provides a glimpse of a future in which telecommunication networks provide not only connectivity, but also GNSS-independent timing and positioning services with unprecedented accuracy and reliability.Comment: 38 pages, 9 figures, 3 table

Chip-based Brillouin processing for carrier recovery in coherent optical communications

Modern fiber-optic coherent communications employ advanced spectrally-efficient modulation formats that require sophisticated narrow linewidth local oscillators (LOs) and complex digital signal processing (DSP). Here, we establish a novel approach to carrier recovery harnessing large-gain stimulated Brillouin scattering (SBS) on a photonic chip for up to 116.82 Gbit/sec self-coherent optical signals, eliminating the need for a separate LO. In contrast to SBS processing on-fiber, our solution provides phase and polarization stability while the narrow SBS linewidth allows for a record-breaking small guardband of ~265 MHz, resulting in higher spectral-efficiency than benchmark self-coherent schemes. This approach reveals comparable performance to state-of-the-art coherent optical receivers without requiring advanced DSP. Our demonstration develops a low-noise and frequency-preserving filter that synchronously regenerates a low-power narrowband optical tone that could relax the requirements on very-high-order modulation signaling and be useful in long-baseline interferometry for precision optical timing or reconstructing a reference tone for quantum-state measurements.Comment: Part of this work has been presented as a postdealine paper at CLEO Pacific-Rim'2017 and OSA Optic

Extending the range of the 802.11G WLAN through improved synchronization techniques

Orthogonal Frequency Division Multiplexing (OFDM) allows for a spectrally efficient means of obtaining high data rates while simultaneously combating the effects of fading. The multi-carrier spectrum of OFDM mandates that the receiver accomplish a number of synchronization tasks to successfully demodulate the OFDM signal, including the critical requirement to synchronize the carrier frequency. Additional synchronization tasks include frame synchronization (packet detection), synchronization of the carrier phase, and symbol timing. Improved receiver synchronization algorithms may hold the prospect of superior performance; specifically allowing successful demodulation by the receiver at an extended range. This thesis discusses several promising synchronization algorithms. Furthermore, a performance analysis of these algorithms is conducted at low signal to noise ratio (SNR) in an AWGN channel using MATLAB.http://archive.org/details/extendingrangeof109453531US Navy (USN) author.Approved for public release; distribution is unlimited

Timing Recovery for DOCSIS 3.1 Upstream OFDMA Signals

Data-Over-Cable Service Interface Specification (DOCSIS) is a global standard for cable communication systems. Before version 3.1, the standard has always specified single-carrier (SC) quadrature-amplitude modulation (QAM) as the modulation scheme. Given that the multi-carrier orthogonal frequency-division multiplexing (OFDM) technique has been increasingly popular and adopted in many wired/wireless communications systems, the newest cable communication standard, DOCSIS 3.1, also introduces OFDM as a major upgrade to improve transmission efficiency. In any digital communication systems, timing synchronization is required to determine and compensate for the timing offset from the transmitter to the receiver. This task is especially crucial and challenging in an OFDM system due to its very high sensitivity to synchronization errors. Although there have been many studies on the topic of OFDM timing synchronization, none of the existing methods are not directly applicable to DOCSIS 3.1 systems. Therefore, the main objective of this research is to develop effective and affordable timing synchronization algorithms for the DOCSIS 3.1 upstream signal. Specifically, three timing synchronization algorithms are proposed to comply and take advantage of the structure of the ranging signal (i.e., the signal used for synchronization purpose) specified in DOCSIS 3.1 standard. The proposed methods are evaluated under a realistic multipath uplink cable channel using computer simulation. The first algorithm makes use of the repetitive pattern of the symbol pairs in the ranging signal. The locations of the symbol pairs are determined by calculating a correlation metric and identifying its maximum value. The second and third algorithms are developed so that they exploit the mirrored symmetry of the binary phase-shift keying (BPSK)-modulated time-domain samples, corresponding to the first non-zero symbol in the ranging signal, and look for the exact location of the symmetry point. The first algorithm, with very low hardware complexity, provides reasonable performance under normal traffic and channel conditions. However its performance under a severe channel condition and heavy traffic is not satisfactory. The second and third algorithms provide much more accurate timing estimation results, even under the severe channel condition and heavy traffic flow. Since the second algorithm requires an enormous increase in hardware complexity, a few options are proposed to reduce the hardware complexity but it is still much higher than the complexity of the first algorithm. Applying the same complexity reduction techniques it is demonstrated that the third algorithm has similar hardware complexity to the first algorithm, while its timing estimation performance remains excellent