Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

The estimation of the Direction of Arrival (DoA) is one of the most critical parameters for target recognition, identification and classification. MUltiple SIgnal Classification (MUSIC) is a powerful technique for DoA estimation. The algorithm requires complex mathematical operations like the computation of the covariance matrix for the input signals, eigenvalue decomposition and signal peak search. All these signal processing operations make real-time and resource-efficient implementation of the MUSIC algorithm on Field Programmable Gate Arrays (FPGAs) a challenge. In this paper, a novel design approach is proposed for the FPGA-implementation of the MUSIC algorithm. This approach enables a significant reduction in both FPGA resources and latency. In more detail, the proposed design enables the estimation of DoA in real-time scenarios in 2μ sec with 30% to 50% fewer resources as compared to existing techniques.The work of Pedro Reviriego was supported in part by the Architecting Intelligent Cost-effective Central Offices to enable 5G Tactile Internet (ACHILLES) through the Spanish Ministry of Economy and Competitivity under Project PID2019-104207RB-I00, in part by the Madrid Government (Comunidad de Madrid-Spain) through the Multiannual Agreement with Universidad Carlos III de Madrid (UC3M) in the line of Excellence of University Professors under Grant EPUC3M21, and in part by the Context of the V Plan Regional de Investigación Científica e Innovación Tecnológica (V PRICIT) (Regional Program of Research and Technological Innovation)

Temporal unpredictability detection of real-time video sequence

Imperial Users onl

FPGA Hardware Implementation of DOA Estimation Algorithm Employing LU Decomposition

In this paper, authors present their work on field-programmable gate array (FPGA) hardware implementation of proposed direction of arrival estimation algorithms employing LU factorization. Both L and U matrices were considered in computing the angle estimates. Hardware implementation was done on a Virtex-5 FPGA and its experimental verification was performed using National Instruments PXI platform which provides hardware modules for data acquisition, RF down-conversion, digitization, etc. A uniform linear array consisting of four antenna elements was deployed at the receiver. LabVIEW FPGA modules with high throughput math functions were used for implementing the proposed algorithms. MATLAB simulations of the proposed algorithms were also performed to validate the efficacy of the proposed algorithms prior to hardware implementation of the same. Both MATLAB simulation and experimental verification establish the superiority of the proposed methods over existing methods reported in the literature, such as QR decomposition-based implementations. FPGA compilation results report low resource usage and faster computation time compared with the QR-based hardware implementation. Performance comparison in terms of estimation accuracy, percentage resource utilization, and processing time is also presented for different data and matrix sizes

Design and application of reconfigurable circuits and systems

Open Acces