4 research outputs found
Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard
This paper addresses the implementation of Reed-
Solomon decoding for battery-powered wireless
devices. The scope of this paper is constrained by the
Digital Media Broadcasting (DMB). The most critical
element of the Reed-Solomon algorithm is implemented
on two different reconfigurable hardware
architectures: an FPGA and a coarse-grained
architecture: the Montium, The remaining parts are
executed on an ARM processor. The results of this
research show that a co-design of the ARM together
with an FPGA or a Montium leads to a substantial
decrease in energy consumption. The energy
consumption of syndrome calculation of the Reed-
Solomon decoding algorithm is estimated for an FPGA
and a Montium by means of simulations. The Montium
proves to be more efficient
Instruction set extensions for software defined radio on a multithreaded processor
Software dened radios, which provide a programmable solu-tion for implementing the physical layer processing of multi-ple communication standards, are widely recognized as one of the most important new technologies for wireless com-munication systems. Emerging communication standards, however, require tremendous processing capabilities to per-form high-bandwidth physical-layer processing in real time. In this paper, we present instruction set extensions for sev-eral important communication algorithms including convo-lutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. The performance bene ts of these extensions are evaluated using a supercom-puter class vectorizing compiler and the Sandblaster low-power multithreaded processor for software dened radio. The proposed instruction set extensions provide signicant performance improvements, while maintaining a high degree of programmability. Categories and Subject Descriptors C.3 [Computer Systems Organization]: Special-purpose and Application-based Systems|Real-time and embedded sys
Low-power instruction-caches design for embedded microprocessors
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