The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study

As DRAM cells continue to shrink, they become more susceptible to retention failures. DRAM cells that permanently exhibit short retention times are fairly easy to identify and repair through the use of memory tests and row and column redundancy. However, the retention time of many cells may vary over time due to a property called Variable Retention Time (VRT). Since these cells intermittently transition between failing and non-failing states, they are particularly difficult to identify through memory tests alone. In addition, the high temperature packaging process may aggravate this problem as the susceptibility of cells to VRT increases after the assembly of DRAM chips. A promising alternative to manufacturetime testing is to detect and mitigate retention failures after the system has become operational. Such a system would require mechanisms to detect and mitigate retention failures in the field, but woul

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee re-liable operation. When deciding the timing parameters, DRAM manufacturers incorporate a very large margin as a provision against two worst-case scenarios. First, due to process varia-tion, some outlier chips are much slower than others and can-not be operated as fast. Second, chips become slower at higher temperatures, and all chips need to operate reliably at the high-est supported (i.e., worst-case) DRAM temperature (85◦C). In this paper, we show that typical DRAM chips operating at typ-ical temperatures (e.g., 55◦C) are capable of providing a much smaller access latency, but are nevertheless forced to operate at the largest latency of the worst-case. Our goal in this paper is to exploit the extra margin that is built into the DRAM timing parameters to improve perfor-mance. Using an FPGA-based testing platform, we first char-acterize the extra margin for 115 DRAM modules from three major manufacturers. Our results demonstrate that it is possi-ble to reduce four of the most critical timing parameters by a minimum/maximum of 17.3%/54.8 % at 55◦C without sac-rificing correctness. Based on this characterization, we pro-pose Adaptive-Latency DRAM (AL-DRAM), a mechanism that adaptively reduces the timing parameters for DRAM modules based on the current operating condition. AL-DRAM does not require any changes to the DRAM chip or its interface. We evaluate AL-DRAM on a real system that allows us to re-configure the timing parameters at runtime. We show that AL-DRAM improves the performance of memory-intensive work-loads by an average of 14 % without introducing any errors. We discuss and show why AL-DRAM does not compromise re-liability. We conclude that dynamically optimizing the DRAM timing parameters can reliably improve system performance. 1

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book