Minimizing internal speedup for performance guaranteed optical packet switches

Providing QoS guarantee for Internet services is very important It evokes the issue that packet switches should provide guaranteed performance (i.e. 100% throughput with bounded worst-case delay). Optical switching technology is widely considered as an excellent solution for packet switches in future networks. However, to achieve guaranteed performance in optical packet switches, an internal speedup is required due to the existence of reconfiguration overhead. How to reduce the internal speedup is the main concern for making these switches practical In this paper, we first derive the internal speedup S as a function of the number of switch configurations N S and the reconfiguration overhead δ, or S=f(N S,δ). We show that the recently proposed ADJUST algorithm is flawed. Based on the internal speedup function we derived, a new algorithm (ADAPTIVE), with time complexity of O((λ-l)N 2logN), is proposed to minimize S. © 2004 IEEE.published_or_final_versio

On optimization of optical packet switches with reconfiguration overhead

Optical packet switching is one of the most promising technologies for carrying IP traffic over WDM optical networks. For optical packet switch (OPS) design, due to the reconfiguration overhead in the switch fabric, packet delay and speedup are two key factors to be considered. Existing scheduling algorithms, DOUBLE [4] and ADAPTIVE [5], make effective tradeoff between these two factors. In this paper, we show that the performance of both DOUBLE and ADAPTIVE, as well as their underlying OPS switch architecture, can be further optimized. Our proposed solutions are shown to effectively reduce both speedup and packet delay at the same time without incurring any extra cost. © 2005 IEEE.published_or_final_versio

Traffic scheduling in non-blocking optical packet switches with minimum delay

For performance guaranteed OPS switches with reconfiguration overhead, it has been shown that packet delay can be minimized by using N switch configurations (where N is the switch size) to schedule the traffic. However, this usually involves an exorbitant speedup requirement, which makes it impractical under current technology. In this paper, a new minimum-delay scheduling algorithm QLEF (Quasi Largest-Entry-First) is proposed. We prove that QLEF pushes the required speedup bound to the lowest known level. As an example, when N=950, QLEF only requires a speedup of S schedule=21.33 instead of 42.25 for MIN [5] and 30.27 for α i-SCALE [8]. This gives a 50% improvement over MIN and 30% over α i-SCALE. © 2005 IEEE.published_or_final_versio

Scheduling optical packet switches with minimum number of configurations

In order to achieve the minimum traffic delay in a performance guaranteed optical packet switch (OPS) with reconfiguration overhead, the switch fabric has to use the minimum number of configurations (i.e. N configurations where N is the switch size) for traffic scheduling. This requires a very high speedup in the switch fabric to compensate for the loss in scheduling efficiency. The high speedup requirement makes the idea of using N configurations (to schedule the traffic) impractical under current technology. In this paper, we propose a new scheduling algorithm called α i-SCALE to lower the speedup required. Compared with the existing MIN algorithm [5], α i- SCALE succeeds in pushing the speedup bound (i.e. worst-case speedup requirement) to a much lower level. For example, when N=200, the speedup bound required to compensate the loss in scheduling efficiency is 30.75 for MIN, whereas 23.45 is sufficient for our α i-SCALE. © 2005 IEEE.published_or_final_versio

Priority Based Switch Allocator in Adaptive Physical Channel Regulator for On Chip Interconnects

Chip multiprocessors (CMPs) are now popular design paradigm for microprocessors due to their power, performance and complexity advantages where a number of relatively simple cores are integrated on a single die. On chip interconnection network (NoC) is an excellent architectural paradigm which offers a stable and generalized communication platform for large scale of chip multiprocessors. The existing model APCR has three regulation schemes designed at switch allocation stage of NoC router pipelining, such as monopolizing, fair-sharing and channel-stealing. Its aim is to fairly allocate physical bandwidth in the form of flit level transmission unit while breaking the conventional assumptions i.e.its size is same as phit size. They have implemented channel-stealing scheme using the existing round-robin scheduler which is a well known scheduling algorithm for providing fairness, which is not an optimal solution. In this thesis, we have extended the efficiency of APCR model and propose three efficient scheduling policies for the channel stealing scheme in order to provide better quality of service (QoS). Our work can be divided into three parts. In the first part, we implemented ratio based scheduling technique in which we keep track of average number of its sent from each input in every cycle. It not only provides fairness among virtual channels (VCs), but also increases the saturation throughput of the network. In the second part, we have implemented an age based scheduling technique where we prioritize the VC, based on the age of the requesting flits. The age of each request is calculated as the difference between the time of injection and the current simulation time. Age based scheduler minimizes the packet latency. In the last part, we implemented a Static-Priority based scheduler. In this case, we arbitrarily assign random priorities to the packets at the time of their injection into the network. In this case, the high priority packets can be forwarded to any of the VCs, whereas the low priority packets can be forwarded to a limited number of VCs. So, basically Static-Priority based scheduler limits the accessibility on the number of VCs depending upon the packet priority. We study the performance metrics such as the average packet latency, and saturation throughput resulted by all the three new scheduling techniques. We demonstrate our simulation results for all three scheduling policies i.e. bit complement, transpose and uniform random considering from very low (no load) to high load injection rates. We evaluate the performance improvement because of our proposed scheduling techniques in APCR comparing with the performance of basic NoC design. The performance is also compared with the results found in monopolizing, fair-sharing and round-robin schemes for channel-stealing of APCR. It is observed from the simulation results using our detailed cycle-accurate simulator that our new scheduling policies implemented in APCR model improves the network throughput by 10% in case of synthetic workloads, compared with the existing round-robin scheme. Also, our scheduling policy in APCR model outperforms the baseline router by 28X under synthetic workloads

Guaranteed Scheduling for Switches with Configuration Overhead

In this paper we present three algorithms that provide performance guarantees for scheduling switches, such as optical switches, with configuration overhead. Each algorithm emulates an unconstrained (zero overhead) switch by accumulating a batch of configuration requests and generating a corresponding schedule for a constrained switch. Speedup is required both to cover the configuration overhead of the switch and to compensate for empty slots left by the scheduling algorithm. Scheduling algorithms are characterized by the number of configurations, Ns , they require to cover a batch of requests, and the speedup required to compensate for empty slots, S min . We show that a well known exact matching algorithm, EXACT, leaves no empty slots (i.e. S min =1), but requires Ns configurations for an N - port switch leading to high overhead or large batches and hence high delay. We present two new algorithms that reduce the number of configurations required substantially. MIN covers a batch of requests in the minimum possible number of configurations, Ns = N , but at the expense of many empty slots, S min 4log 2 N . DOUBLE strikes a balance, requiring twice as many configurations, Ns =2N , while reducing the number of empty slots so that S min =2. We show that DOUBLE offers the lowest required speedup to emulate an unconstrained switch across a wide range of port count and delay

Guaranteed scheduling for switches with configuration overhead

Abstract—In this paper, we present three algorithms that provide performance guarantees for scheduling switches, such as optical switches, with configuration overhead. Each algorithm emulates an unconstrained (zero overhead) switch by accumulating a batch of configuration requests and generating a corresponding schedule for a constrained switch. Speedup is required both to cover the configuration overhead of the switch and to compensate for empty slots left by the scheduling algorithm. Scheduling algorithms are characterized by the number of configurations they require to cover a batch of requests and the speedup required to compensate for empty slots ���. Initially, all switch reconfiguration is assumed to occur simultaneously. We show that a well-known exact matching algorithm, EXACT, leaves no empty slots (i.e., �� � aI), but requires P configurations for an-port switch leading to high configuration overhead or large batches and, hence, high delay. We present two new algorithms that reduce the number of configurations required substantially. MIN covers a batch of requests in the minimum possible number of configurations, a, but at the expense of many empty slots, �� � R���P. DOUBLE strikes a balance, requiring twice as many configurations, a P, while reducing the number of empty slots so that �� � aP. Loosening the restriction on reconfiguration times, the scheduling problem is cast as an open shop. The best known practical scheduling algorithm for open shops, list scheduling (LIST), gives the same emulation requirements as DOUBLE. Therefore, we conclude that our architecture gains no advantages from allowing arbitrary switch reconfiguration. Finally, we show that DOUBLE and LIST offer the lowest required speedup to emulate an unconstrained switch across a wide range of port count and delay. Index Terms—Optical switches, packet switching. NOMENCLATUR